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I have 2 time domain clocks (completely independent) and a bit stream (single bit)

The first clocks is at 12.29 MHz .

I want to asynchronously reclock it to a second time domain.

Meta stability is solved using 2 flipflops (better 3?).
For data loss , I understood that I need the second clock to be at least twice the speed of the first clock (so 24.6MHz).

Using the above, can I expect 100% reliability ?

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  • \$\begingroup\$ You say you want to reclock "it". You want to reclock the 12.29 MHz clock to move the edges into a new clock domain? \$\endgroup\$ – crj11 Jun 5 '18 at 15:31
  • \$\begingroup\$ yes I want the edges of the first clock to move in the second time domain without any data loss \$\endgroup\$ – Johan B. Jun 5 '18 at 15:32
  • \$\begingroup\$ You want to sample signals into the 2nd domain that originate in the 1st domain... not sample the 1st domain clock, right? \$\endgroup\$ – CapnJJ Jun 5 '18 at 15:49
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You can never expect 100% reliability, but you can expect 99.99999...% reliability.

As you can see in the picture below (from here), the MTBF is proportional to the clock frequency and number of stages. It also depends on the "metastable resoltuion time", which is shorter for faster logic.

With fast enough logic and enough synchronization stages, you can design for one failure in the lifetime of the universe, on average. Keep in mind that if you are running more than one device, you have to divide your MTBF by the total number of number of devices.

Also, make sure to stay away from Infinite Improbability Drives.

EDIT:

As for the reliability of a 2X clock, you could be unlucky and be aligned with the rising and falling edge of the slow clock and have both synchronizations settle to the same level, thus missing the high or low portion of the slow clock. If the fast clock period is shorter than the minimum high or low time of the slow clock minus the setup and hold time for the synchronizing FF, you are guaranteed to see at least one fast clock period at the output of the synchronizer for each level of the slow clock.

enter image description here

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  • \$\begingroup\$ Yes understood about meta stability and MTBF. How about dataloss with the second clock being 2x speed ? \$\endgroup\$ – Johan B. Jun 5 '18 at 16:52
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Here is an equation I copied from a site that talks about metastability

metastability Equations

To determine how often a Flip Flop will go to an undefined state, plug the data into one of these equations to calculate the MTBF. The first equation is the general calculation, while the second uses a worst case input data rate of half the clock frequency.

metastability equations

metastability Definitions

MTBF: Mean Time Between Failure
FD: Data Frequency
FC: Clock Frequency
TP: Flip Flop Propagation Delay
tr: Resolve Time
dt: Delay Time between Clocks [symbol delta t]
tsu: Device Setup Time
g: Flip FLop Resolution Time [symbol gama]

These are device dependent. Resolve time (among others) has to be looked up, via the data sheet (if it's provided). As a rule: The faster the flip flop used, the better the MTBF for a given circuit. The faster device families have lower Set-up and Hold times. This reduces the window of occurrence.

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    \$\begingroup\$ Please post text as text. Please don't post text as screenshots. Text is searchable, but screenshots aren't. \$\endgroup\$ – Nick Alexeev Jun 5 '18 at 23:36

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