# Bias T to level shift output from oscillator

I am using XOR gate HMC851LC3C to get an ultra-short pulse (200ps range). This logic gate requires inputs in the range of -2.5V to 0.5V. However, RF signals from my oscillator is sine wave -1V to 1V. I want to shift the range of this oscillator output to be -0.5 offset which means to -1.5V to 0.5V in order to satisfy the requirement of the logic gate. My question is, can I use a bias tee and apply sine waves on one side, -0.5V on the other side of the tee. Is this possible and will it change the jittering of the oscillator output after the tee?

Thank you datasheet of HMC851 logic gate

• You say the logic gate " requires inputs in the range of -2.5V to 0.5V," but -2.5 V is below the absolute minimum input voltage range according to the datasheet you linked to. – The Photon Jun 5 '18 at 17:12
• I think I am confused what has been said in the datasheet. If you look at the Max Ratings on couple last pages, it said -2.5V to 0.5V – Lac Jun 5 '18 at 19:09
• I'm looking at Absolute Maximum Ratings on page 4. It says input signals "-2 V to +0.5 V". These are the limits to avoid damaging the part. On page 1 there are recommended operating conditions (how you should use the part for it to behave as advertised) giving input low voltage -1.0 to 0.0 V. If you make the low voltage below -2.0 you could damage the part. If you make the low voltage below -1.0 V, the behavior might not be what's specified in the datasheet. – The Photon Jun 5 '18 at 20:08

There is a solution that's even simpler than what you proposed.

Notice that the inputs of this gate are differential. And the recommended logic low voltage includes 0 V.

That means if you bias one side of the differential input at 0 V, and apply a pure AC input (biased at 0 V) on the other side of the differential input, say 1 V peak-peak to avoid exceeding the maximum recommended high logic level (0.5 V), the gate should interpret this as a valid toggling logic input.

So you don't need a bias tee, just a dc-blocking capacitor (and a 3 dB attenuator) between your 2 V peak-peak oscillator and the HMC851 logic input.

simulate this circuit – Schematic created using CircuitLab

• Would this affect the duty cycle of the output? – crj11 Jun 5 '18 at 17:26
• It looks really strange in the datasheet to see the input Vlow between -1 and 0 and Vhigh between -0.5 and 0.5. They overlap. How would the gate determine a signal at 0V? – a concerned citizen Jun 5 '18 at 17:26
• @aconcernedcitizen, the input is differential so if AP>AN that would be a "1" and if AP<AN it will be a "0". Unfortunately it's not real clear what the minimum input amplitude is --- and the plot labelled "Amplitude vs input power" appears messed up, probably the labels for the different curves are switched around. – The Photon Jun 5 '18 at 17:29
• @crj11, if AN is at 0 V and AP gets a sine wave biased at 0 V, the output should have 50% d.c. Of course there will be some error. – The Photon Jun 5 '18 at 17:30
• Buffering means pass the signal through a digital buffer. The advantage would be to have faster edges at the input to the XOR gate. As a start, consider something like MC100EP16, although you might be able to find something faster. – The Photon Jun 6 '18 at 17:08