If this is a buffer, why use an AND gate, aside from better availability of that gate in a single package? This is on an Analog Devices SHARC eval board.

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3 Answers 3


This is a buffer. Two gates means twice the output current. But why use AND gates instead of buffers, you might ask? I was originally going to say that they probably used one or two AND gates elsewhere in the circuit and just popped down a single quad AND gate chip, using two of the AND gates as buffers instead of calling for an actual buffer to save board space and parts count. However, it seems they are the single gate variety. So I presume they had a lot of AND gate chips on hand for whatever reason - perhaps they are used elsewhere in the circuit, or in other designs manufactured on the same production line - and they didn't want to pay for another line item/part feeder on the pick and place machine, so they just specified more AND gates instead of some AND gates and some buffers.

One thing to note about using two AND gates (or another two input logic gate) in this way instead of buffers (or inverters) is that there are twice as many input pins, so the input capacitance will be double. This probably won't be an issue in most cases. If it could possibly be an issue, tie one input high (or low, depending on the gate) instead of connecting both to the input signal.

Edit: looks like one of them is marked DNP, and hence may be an empty footprint on the board. I presume this was done just in case one gate couldn't provide sufficient drive strength, they could add a second without having to re-spin the board.

  • 1
    \$\begingroup\$ Regarding two gates means twice the output current, that's incorrect. There aren't actually two AND gates in the circuit. The schematic and PCB allow either to be used, but only U9 is fitted, and U10 is marked as "DNP" (Do Not Place). Typically this would be done for testing, or to have a backup device available in case there are problems getting hold of the U9 device. If you actually connected the outputs of two devices together, the result would be that they'd burn out trying to fight each other, not that you'd get twice the output current. \$\endgroup\$
    – Graham
    Commented Jun 6, 2018 at 9:38
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    \$\begingroup\$ Assuming they pull in the same direction, then they would not fight each other. They're both CMOS, the output transistors will essentially just be in be in parallel. Good point about the DNP annotation, though. I presume they put two footprints on there just in case they needed more drive strength than one could provide. \$\endgroup\$ Commented Jun 6, 2018 at 10:09
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    \$\begingroup\$ Fair point on them being CMOS - you can parallel FETs/MOSFETS to get more current, so that would work. TTL certainly wouldn't, because BJTs don't work that way. Although I still wouldn't recommend it, because the switching times won't be exactly the same, and that will give brief but huge current spikes for the short periods where they aren't both in the same state. Not enough to kill anything immediately, but it won't help lifespan, and those current spikes will create real problems with EMC. \$\endgroup\$
    – Graham
    Commented Jun 6, 2018 at 11:28
  • \$\begingroup\$ @Graham: Having both inputs of an "AND" gate tied to a signal source would likely nearly double the loading on that source with having one input tied to that source and the other strapped high. \$\endgroup\$
    – supercat
    Commented Jun 6, 2018 at 15:10
  • \$\begingroup\$ @supercat That's true, but not really relevant to what I was saying about both outputs of the two separate "AND" gates. Still, it's another possible improvement to the circuit. \$\endgroup\$
    – Graham
    Commented Jun 6, 2018 at 15:44

The designers have probably chosen the AND gates because of availability or some other such convenience. Maybe they had the AND gates on the bill of materials for that board already.

The gates are used as a buffer for driving the cable. The two gates can output more current than the part which generates the signal initially.

There are ICs that do just buffering without logic functions (SN74LVC2G34, for example.)

  • \$\begingroup\$ "because of availability or some other such convenience"... They call that "Design For Manufacturing" (DFM), but who knew anyone really did that? Probably a new-hire's 6-Sigma project came up with that (final) board design... I like it, mostly :) \$\endgroup\$
    – CapnJJ
    Commented Jun 6, 2018 at 16:09

SPDIF is designed to drive 1Vp-p from 75 ohm source into a 75 ohm load.

Having worked out the current required from the driver, presumably the designers decided that was the cheapest way (or smallest in terms of PCB space, or otherwise optimal in their design) way to supply it.


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