I have a design that instantiates a Memory and a Ring oscillator which I am excluding from synthesis by making them black boxes.(Not specifying explicitly, but instantiating an empty module with only port directions). I know I need lef and lib for the two blocks finally but I only need netlist for the surrounding logic to simulate. I know that synthesis tool will remove any logic that doesn't end in an output. But what about the paths that are coming out of and into these black boxes? Will it see them as no logic and remove them. If so what should I do to preserve them?
If you define the module as 'black box' the synthesis stool will not optimize it away or use it to optimize signals away.
I can't remember the exact phrase but it was something like
// synopsys syn_black_box