I’ve been baffled about this for years. Why is the hardware design industry pushing so hard on the use of axi bus for communicating with cores and peripherals that don’t gain any advantage from its use in an FPGA?
What’s the advantage of using axi bus over a more signal efficient buses? Even axi lite seems like overkill most of the time. I could guess if you are close to the cpu pipeline running at 3 GHz that maybe you have to use something like that? but I have yet to find an fpga from Xilinx or altera that runs even 10 % of that rate and yet there’s the axi bus requirement for all of Vivado IP cores.
I look at Xilinx Vivado and I see axi bus every where with strange latent wrappers around more normal local buses just to translate it back to axi bus. I don’t know. It just all seems strange to me.
As a logic designer I really don’t have a choice to follow the axi convention when they already configure every core that way. Otherwise I would spend all of my time removing axi wrapper files.
I guess I’m just wondering what they see in axi bus that I don’t? Is this just some weird conspiracy to keep everybody busy wiring buses together and to sell larger more expensive FPGA’s that do exactly the same thing?