I’ve been baffled about this for years. Why is the hardware design industry pushing so hard on the use of axi bus for communicating with cores and peripherals that don’t gain any advantage from its use in an FPGA?

What’s the advantage of using axi bus over a more signal efficient buses? Even axi lite seems like overkill most of the time. I could guess if you are close to the cpu pipeline running at 3 GHz that maybe you have to use something like that? but I have yet to find an fpga from Xilinx or altera that runs even 10 % of that rate and yet there’s the axi bus requirement for all of Vivado IP cores.

I look at Xilinx Vivado and I see axi bus every where with strange latent wrappers around more normal local buses just to translate it back to axi bus. I don’t know. It just all seems strange to me.

As a logic designer I really don’t have a choice to follow the axi convention when they already configure every core that way. Otherwise I would spend all of my time removing axi wrapper files.

I guess I’m just wondering what they see in axi bus that I don’t? Is this just some weird conspiracy to keep everybody busy wiring buses together and to sell larger more expensive FPGA’s that do exactly the same thing?

  • 5
    \$\begingroup\$ A more cynical observer of the FPGA market might conclude that tools from all major vendors have been gravitating towards abstracting away all low level decisions in order to allow software coders to write hardware. This abstraction is done at any cost, even if it gives abominable hardware. Not me, though, just a more cynical person. \$\endgroup\$ – DonFusili Jun 6 '18 at 9:00
  • \$\begingroup\$ That’s true as well. \$\endgroup\$ – Bill Moore Jun 6 '18 at 9:02
  • 1
    \$\begingroup\$ Then the software coders decide it doesn’t work so well to covert software into hardware logic with a behavioral compiler and the GPU wins instead... \$\endgroup\$ – Bill Moore Jun 6 '18 at 9:07
  • \$\begingroup\$ AMBA use, in-general, is driven by the relatively simple nature of the bus protocol combined with the prevalent use of ARM microprocessors in designs. Don't forget to use your AHB and APB busses (where it makes sense) too. \$\endgroup\$ – CapnJJ Jun 6 '18 at 15:49
  • \$\begingroup\$ And, while originally only found in SOCs, now, since ARM cores are avaialable in FPGAs too, there is a "natural" push to create IP with AMBA interfaces for ease of integration. \$\endgroup\$ – CapnJJ Jun 6 '18 at 16:00

AXI bus is efficient for high throughput data transfers. If you have simple peripherals the procedure is to use an AXI to APB converter and drive all your simple peripherals from the APB bus.

AXI is great if you have e.g. an USB/PCIe/Ethernet core. You add a AXI master and it pushes the data straight to memory, using very efficient data bursts.

I have used AXI for many years and found that nobody in ASIC land implements the full AXI specs on their chip, even within a company. The most complex parts are dropped to reduce logic, which gives interesting stories if AXI IP comes together...

What caught my eye is that a lot of smaller cores (even those from the manufacturer who has set the AXI standard) do not use the full AXI capabilities. The core datasheets I have seen say "You will only see single transfers cycles coming out of the core."

| improve this answer | |
  • \$\begingroup\$ personally, I think IBM’s PowerPC core bus is more efficient than any of Amba buses specified by arm... \$\endgroup\$ – Bill Moore Jun 6 '18 at 9:21
  • \$\begingroup\$ my project manager from 10 years ago was complaining that every project based on AXI bus turned into a disaster for the company. \$\endgroup\$ – Bill Moore Jun 6 '18 at 9:45
  • 1
    \$\begingroup\$ @BillMoore I found that AXI looks deceptively easy, but it is far from! You need some very competent engineers to see all the pitfalls and corners cases and get it right. \$\endgroup\$ – Oldfart Jun 6 '18 at 9:56
  • \$\begingroup\$ We had them... i think the problem with it is that it spreads things out too much to the extent that you need automation tools to complete even simple tasks with axi... \$\endgroup\$ – Bill Moore Jun 6 '18 at 10:04
  • \$\begingroup\$ the fun part is that the complexity overhead was understood and AXI4-lite was specified … just to, again, be complex enough to raise the desire to not fully implement it. Looking forward to AXI4.1–Diet with less states :) \$\endgroup\$ – Marcus Müller Jun 6 '18 at 11:51

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.