I've been trying to understand how the dc bias is removed at the ouput inside an op amp. Below circuit seems to work
enter image description here

Some explanation is given below by the author

To shift the output dc level to zero, level translator circuits are used. An emitter follower with voltage divider is the simplest form of level translator as shown in fig. 2.

Thus a dc voltage at the base of Q produces 0V dc at the output. It is decided by R1 and R2.

But I don't quite get how R1 and R2 manage to maintain 0V at the output no matter what dc value we put at the Input. As the Input changes, \$V_{CE}\$ of the transistor \$Q\$ varies on the load line, so I don't see how the o/p can stay at 0V. Appreciate any help.

  • \$\begingroup\$ My work so far : KVL through output loop gives $$V_{CC}-V_{CE} - I_C(R_1+R_2) +V_{EE}= 0 $$ \$\endgroup\$ – AgentS Jun 7 '18 at 5:03
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    \$\begingroup\$ do not put additional information into comments .... please add the info to your question and delete the comment \$\endgroup\$ – jsotola Jun 7 '18 at 5:04
  • \$\begingroup\$ Ohk.. sorry I thought my question was getting too big, I'll try adding it to the question :) \$\endgroup\$ – AgentS Jun 7 '18 at 5:05
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    \$\begingroup\$ You must have left some context out of what you quoted from your book. There is one particular input voltage that produces 0 V output. Other input voltages will produce different output voltages. \$\endgroup\$ – The Photon Jun 7 '18 at 5:05
  • \$\begingroup\$ @ThePhoton I copied the circuit and explanation from nptel.ac.in/courses/117107094/lecturers/lecture_5/… \$\endgroup\$ – AgentS Jun 7 '18 at 5:06

There is one particular input voltage that produces 0 V output. Other input voltages will produce different output voltages.

From comments, you said you got this circuit from course notes about op-amp design. This is the 3rd stage of an example op-amp design.

In this context, you would design the circuit (choose R1 and R2) so that the output voltage is 0 when the input voltage is at the bias point reached when the op-amp's input voltage is (exactly) 0 V. Then any change in the whole circuit's input voltage will shift the output above or below 0.

If you want to analyze the circuit using KVL, the more useful loop to consider is the one that incudes the source driving this circuit, Q's b-e junction, R1, R2, and the -VEE source.

  • \$\begingroup\$ You're my savior! I get it! $$V_b-V_{BE}-I_CR_1 = 0; I_CR1+V_{EE}=0$$ Above two equations give the ratio of resistors we must choose to maintain 0V for a particular \$V_b\$. This \$V_b\$ is actually known to us because it comes from the previous stage. Awesome! Thanks again :) \$\endgroup\$ – AgentS Jun 7 '18 at 5:26

DC bias for Vb is chosen such that ...


Although this design is less efficient than others since R1+R2 raises output impedance yet must be much smaller than load R.

  • \$\begingroup\$ +1 for making me remember what pipe symbols mean (vertical bars) ... lol \$\endgroup\$ – jsotola Jun 7 '18 at 5:13
  • \$\begingroup\$ Ahh so as @The Photon says the output is 0V only for one particular dc Input. I think I know how the condition given by you produces the virtual ground at the output. Let me grab pen and paper and work a bit. Thank you :) \$\endgroup\$ – AgentS Jun 7 '18 at 5:15

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