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Here is the setup :

schematic

simulate this circuit – Schematic created using CircuitLab

RX channel is routed as 100ohm controlled impedance. FPGA input pins are LVDS IOs. I want to apply a DC bias of +1.2V at the FPGA. can I simply add 50ohm pull-ups to +1.2V on each of the differential lines? Thanks.

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If you disable the internal termination, you could externally terminate to 1.2V / 50 ohms on each input. However, with internal 100 ohm termination enabled, you should use much higher value resistors to set the common mode voltage as shown below from this Maxim app note. The larger resistors set the common mode voltage, but do not interfere with the termination.

Your signal integrity should be a little better with internal termination, so the higher value external resistors are probably the best solution.

enter image description here

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  • \$\begingroup\$ Excellent...that makes sense. Thanks crj11! \$\endgroup\$ – ErikC Jun 7 '18 at 18:21

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