I'm testing a few different circuits for basic gates, made in DTL (Diode-Transistor Logic). One of the more popular layouts for NAND seems to be:
This is actually a NOT gate, but can be easily extended into NAND by adding more inputs (square wave on schematic). When I actually created the circuit, I've noticed that the rise and fall times are asymmetric. Initially I thought it might be my oscilloscope's capacitance, but it shows even in simulations. To be precise: although fall time of the gate is very small (a few microseconds at most), rise time is pretty large - 100us in my circuit, >50us in simulations. Why is that? I found that changing 47k resistor into smaller one helps, but I'd prefer to know the underlying reason.
I'm confused that the 47k is the culprit, because assuming the time constant is roughly RC, then C would have to be 100us/47kohm = 2nF, which is much too high for wire, oscilloscope's or other parasitic capacitances. Perhaps there's some effect I'm not aware of in the BJT itself, but from my research their parasitic capacitances are typically a few pF, which doesn't explain the problem either.
Effects of simulation: