I'm testing a few different circuits for basic gates, made in DTL (Diode-Transistor Logic). One of the more popular layouts for NAND seems to be:


simulate this circuit – Schematic created using CircuitLab

This is actually a NOT gate, but can be easily extended into NAND by adding more inputs (square wave on schematic). When I actually created the circuit, I've noticed that the rise and fall times are asymmetric. Initially I thought it might be my oscilloscope's capacitance, but it shows even in simulations. To be precise: although fall time of the gate is very small (a few microseconds at most), rise time is pretty large - 100us in my circuit, >50us in simulations. Why is that? I found that changing 47k resistor into smaller one helps, but I'd prefer to know the underlying reason.

I'm confused that the 47k is the culprit, because assuming the time constant is roughly RC, then C would have to be 100us/47kohm = 2nF, which is much too high for wire, oscilloscope's or other parasitic capacitances. Perhaps there's some effect I'm not aware of in the BJT itself, but from my research their parasitic capacitances are typically a few pF, which doesn't explain the problem either.

Effects of simulation:

enter image description here

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    \$\begingroup\$ It takes a while for the base-emitter voltage to drop as you don't really have an Ohmic path for the base when the BJT goes off. \$\endgroup\$
    – jonk
    Jun 8 '18 at 0:14
  • \$\begingroup\$ Hmm, that makes sense. I added an extra diode from V2 to base, and rise seems to improve to 5us. Why does the collector resistor make a difference though? Also, is there a formula or model that would help me estimate the effect? \$\endgroup\$
    – akrasuski1
    Jun 8 '18 at 0:49
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    \$\begingroup\$ When D1's anode is pulled hard low with only a trickle current from R1, and D1's cathode is still sitting close to where it was (charge storage in the BJT) with no Ohmic path to discharge, this charge is still able to supply recombination to allow collector current to continue and hold the output low. As the stored charge gets consumed, the voltage discharges and that lowers the available recombination current, lowering the collector current... etc. A smaller-valued collector resistor will of course make all that happen faster. \$\endgroup\$
    – jonk
    Jun 8 '18 at 1:02
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    \$\begingroup\$ In a very rough way it is predictable. There is usually something like 10−30pF of stored charge in the BJT junctions. Don't forget that the base recombination current will be about β less than the collector current, so a lot of collector current can flow while only consuming a small part of the stored charge. That stored charge goes a long way. So it works out to something like a time constant of about \$\tau\approx R_\text{C}\cdot C_\text{BJT}\cdot \beta\$. The effective value of the capacitance depends on both the base-emitter and base-collector stored charges, mostly the BC junction. \$\endgroup\$
    – jonk
    Jun 8 '18 at 1:19
  • \$\begingroup\$ Pull up your Spice model and find the parameter CJC and read off its value. Also, look for BF (forward beta.) Those should get you close, I think. \$\endgroup\$
    – jonk
    Jun 8 '18 at 1:47

Read up on Miller Effect. The presence of D1 makes the transistor on/off behavior be highly imbalanced, even as the Cob (capacitance base-collector) demands for charge remains the same whether turning on or turning off.

By the way, this is a superb question to show the trickery imposed by diodes.


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