What is the best practice or method for synchronizing stimuli input and output with a sequential logic block in VHDL?
I am currently running only behavioral simulations, but I want to make sure my test bench will also work appropriately with timing simulations. I am testing various entities I am writing for handling modular addition/multiplication and a divider before I connect them all together. All sequential logic is written to use the rising edge of the clock.
I was originally providing stimuli at rising edge of the clock at the start of the simulation and waiting for whole multiples of the clock period before checking the results, however, I found that the logic would miss some inputs or take a cycle longer than expected. I've since come to the conclusion that, since inputs need to be stable at the rising edge of the clock, I should be changing stimuli only at the falling edge of the clock. I am now using a wait statement to align with the falling edge of clock and, for logic that take a well-defined number of cycles, wait for the appropriate number of clock periods and check the results. This seems to fix the issues I was having, but is this a recommended practice or should I use a different approach?
Also, when waiting upon output signals such as a ready or ack signal, should I combine that with a wait until rising_edge() and ready = '1', or keep everything, output and input, aligned on the falling edge? Currently, using rising edge for outputs seems to be working.