When the voltage on node n-mosfet is a Logic 1, the complementary Logic 0 is applied to node active-low n-mosfet, allowing both transistors to conduct and pass the signal at IN to OUT. When the voltage on node active-low n-mosfet is a Logic 0, the complementary Logic 1 is applied to node n-mosfet, turning both transistors off and forcing a high-impedance condition on both the IN and OUT nodes, but that not the case here, the output behaves independent of what happens at the gates. I expect to have zero voltage at the out put when the voltage at the p-mosfet is high. Am i doing something wrong? enter image description here

  • \$\begingroup\$ What voltage levels are you running? A mosfet needs a minimum threshold at the gate to work. \$\endgroup\$ – Sven B Jun 10 '18 at 8:51
  • \$\begingroup\$ Also, the bulk nodes may need to be properly connected, 3-terminal mosfets are not symmetrical devices. \$\endgroup\$ – Sven B Jun 10 '18 at 8:55
  • \$\begingroup\$ @SvenB The threshold voltage is 1[V] the clock and AC source are running above this threshold voltage say 2.5 [V] and 5 [V]. I have only three terminals i can't change the component. I think the bulk is connected internally to the gate i ain't really sure. \$\endgroup\$ – Sam Farjamirad Jun 10 '18 at 9:01
  • \$\begingroup\$ Is the right component (blue) a voltage source by any chance? I didn't see at first because of the highlight. In that case the right voltage is fixed by the voltage source, while the left voltage is fixed to 0V by the ground connection and you won't see any effect. \$\endgroup\$ – Sven B Jun 10 '18 at 19:37
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    \$\begingroup\$ Your schematic will close a switch between ground and a voltage source. You won't see anything because both voltages are fixed. Connect a resistor between ground and the TG and measure the voltage across that. \$\endgroup\$ – Sven B Jun 12 '18 at 21:08

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