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![enter image description here](https://i.stack.imgur.com/JzQ6r.jpg)

As you see in the picture above, diode voltage drop is 0V, and the monostable multivibrator is made in CMOS technology with protection diodes. I have problem finding the output of this circuit in some nodes.
So, when the input signal is zero, multivibrator is in stable state, Ve=0, Vd=0, Va=Vdd(logic 1), Vb=Vdd(logic 1).
When the input signal kicks in, I get Va=0, Vb(0+)=0 starting to charge towards logic gate voltage, and Ve=Vdd.
How does logic 1 on Ve influence the capacitor C2 and resistor R2, and any hint on what will happen after NOR gates switch again?

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This circuit relies on inverted edge RC delay from rail to mid voltage threshold for trigger (R1C1=T1)

That leading edge then uses that period to charge up C2 using the low dynamic resistance of D which I refer to as T2= ESR(D)*C2 < R1C1. We choose T1 and T2 so that T1 is bigger yet insignificant compared to the desired stretched output pulse of T3 when T1 has timed out and D is no longer conducting leaving the decay time of T3=R2*C2.

Edge triggered 1-shot (monostable)

T3>>T1>>T2 means the output pulse width of 1 shot comes from the decay of R2C2 but the edge trigger detector R1C1 is long enough to charge up C2 with ESR(D)

This is easily satisfied since C2 is shared by D to charge and R2 to discharge and the ESR of all diodes is roughly 0.5 to 1/Pd [Ω] and most circuit boards are reliable to use with xx MΩ so very wide range of pulse widths is possible with CMOS using analog RC delays before we need to consider binary counters.

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