I've been trying to understand the working of DRAM chips but apparently in a lot of confusion. Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single bank and a byte out of a chip altogether? And out of the 8 bytes coming out of a channel, how does the memory controller accesses only one byte?


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DRAM is organised in a multi-level hierarchy, and knowing the correct terminology for the various layers is key to making sense of it, so I'll briefly recap them to make sure we are on the same page. (This is obviously only talking about the straightforward textbook case, and not considering things like ECC.)

On the lowest level, there is the bank, which is the physical 2D array of cells (capacitors/access transistors) and the word lines and bit lines connecting them. There is one row buffer per bank, which is followed by a column decoder to select – indeed – only one bit from the row.

Eight banks per chip makes for eight data output pins per chip. Eight of these chips would then be combined to make up a rank with 64 output bits. In the case of DIMMs, each physical memory module consists of at least one such rank. For multiple-rank DIMMs, the chips that make up the different ranks share the same command and data lines, so only one rank can use the bus at any moment in time (there are chip-select lines to address them).

Finally, a channel describes the complete system of one or more ranks and the command/data busses connecting them. As far as the low-level signalling is concerned, each channel is an entirely separate bus, so different accesses never conflict, etc.

As to your question about selecting only a single byte: The memory controller is free to handle those 64 bit chunks of data in whichever way is the most appropriate. In theory, it could just include a mux to select the appropriate byte of data to read. In modern processors, however, all memory accesses are typically done in units of cache line width (64 bytes) anyway, so all the bits would be forwarded to the cache subsystem. Even if only reading one byte into a register, the whole cache line would be fetched first.

  • \$\begingroup\$ so, by using multiplexers, one can obtain a single byte from a channel, right? So when the 64 bits reach memory controller, memory controller then multiplexes only one byte and it sent to the processor. Am i right? Also how does only one byte get selected? are there some tri-state buffers to control it after being multiplexed. and if multiplexers are really present, how about when the processor needs complete 8 bytes? \$\endgroup\$
    – Rajat
    Jun 11, 2018 at 15:34
  • \$\begingroup\$ In the modern processors, if all the 64 bytes are read, how does processor operates on only one byte(eg. reading a character literal) \$\endgroup\$
    – Rajat
    Jun 11, 2018 at 15:47
  • \$\begingroup\$ In a modern system, the interface to memory is usually in terms of whole cache lines. Too much overhead to do single byte operations. It's also not possible to read one single byte. You read all 64 bits and discard what you don't need. For writing, there are usually byte enables that mask which bytes to update, the rest are discarded. \$\endgroup\$ Jun 11, 2018 at 20:17
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    \$\begingroup\$ But the thing to remember is that the CPU only operates on the L1 cache. If the data isn't in the cache, then the memory controller goes and fetches a whole cache line from RAM. When a cache line is evicted from cache, it gets written back to memory of it's dirty (cache lines are marked as dirty on write) \$\endgroup\$ Jun 11, 2018 at 20:20

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