# how to initialize a vector of registers in verilog?

I want to initialize the following 16-bit registers in my module.

reg [15:0] coefficient[4:0];


I used concatenation operator to do this:

reg [15:0] coefficient[4:0] = {16'd26, 16'd270, 16'd734, 16'd21, 16'd90};


but I simulate it with ISE, I receive this error:

constant value of constant expression must be used for initialization


how can I fix it??

EDIT: because initial is not synthesizable, I didn't use that. is there another way??

I wanted to suggest you use System Verilog but I don't think ISE supports that. (I went through the file settings and I could not find it).

You then have to use an initial statement:

initial
begin
coefficient[0] = 16'd26;
coefficient[1] = 16'd270;
...
end

• I don't want to use initial since it is not synthesizable. I have to use Verilog. because it is a homework! – Fatemeh Karimi Jun 11 '18 at 15:05
• @FatemehKarimi, why do you think this use of initial is not synthesizable? – The Photon Jun 11 '18 at 15:38
• @ThePhoton I read it on internet, that initial is not synthesizable. – Fatemeh Karimi Jun 11 '18 at 15:38
• @FatemehKarimi, using initial to initialize registers or memories is absolutely synthesizable. Using initial to launch a sequence of transitions (like is often done in a testbench) is not synthesizable. – The Photon Jun 11 '18 at 15:42
• @ThePhoton then the problem is done! you can write an answer and I will accept it – Fatemeh Karimi Jun 11 '18 at 15:44

You should use an explicit value at reset. This is compatible with both ASIC and FPGA implementation. Additionally, it allows for a clean reset if needed as there is no guarantee otherwise that coefficient would return to its first state. For example:

always @(negedge nRESET) begin
coefficient[0] <= 16'd26;
coefficient[1] <= 16'd270;
...
end


You may also want to look at this old question.

• If coefficient ends up being a constant, then doing this alone will result in a whole lot of logic that could have been optimized out. However, this is definitely a good idea in combination with an initial block. – alex.forencich Jun 11 '18 at 19:07
• @alex.forencich The problem, I believe (although could be wrong), is that using the initial block leaves it to the synthesis tool to decide at what stage "coefficient" is set. If you have a warm reset, for example, what value does "coefficient" take compared to a power up reset? Using a defined reset value is the safest way, and the only way for an ASIC. – awjlogan Jun 11 '18 at 20:07