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I want to control a H-bridge using an ATMega2560. The goal is to produce output with +-18V for driving a Merklin H0 digital train set.

Given the voltage and current needed for the trains it is crucial that the H-bridge never ever goes into a shortcut state. And since software is always buggy I don't want to rely on the ATMega to switch the pins correctly. Instead I want to add some hardware between the ATMega and the H-bridge that does the following:

  1. turn the H-bridge off on illegal inputs
  2. when transitioning from one state to another ensure that the H-bridge first gets an off signal before an on signal for the opposite switch.

I have a lot of 74HTCxx chips around so I can implement logic functions with them.

My question now is: How do I make the H-bridge foolproof? How do I ensure the off-before-on transition for the output signals? Can I use gate switch times to delay on signals sufficiently? Or do I need a clock signal and flip-flops to implement discrete transitions from one state to another?

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    \$\begingroup\$ If software is always buggy you're doing it wrong. :) \$\endgroup\$ – DiBosco Jun 11 '18 at 14:53
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Try this: -

enter image description here

From here based on my answer here. Diagrams modified to correct a defect.

And now with another simplification to remove the inverters: -

enter image description here

Both AND and NOR should be schmitt trigger types.

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  • \$\begingroup\$ Shouldn't the falling edge also show a curve? -- I don't have any schmitt trigger and/nor gates so I will go with the first schematic. I was thinking of the problems as having 4 inputs and 4 outputs. But it makes much more sense to generate the complementary signals from a single input. Now I only have to add an AND gate to each output for an enable signal. Saves 2 pins and eliminates illegal inputs as well. \$\endgroup\$ – Goswin von Brederlow Jun 12 '18 at 6:56
  • \$\begingroup\$ @GoswinvonBrederlow yes, it should have an exponential decay. I will fix it. \$\endgroup\$ – Andy aka Jun 12 '18 at 8:15
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    \$\begingroup\$ The first version can be optimized for number of IC by replacing the NOR gate with AND gate and inverted inputs. The delayed inverted signal is already there so it will need only an inverter for the upper path. Six inverter gates and four AND gates , two chips for a full bridge. \$\endgroup\$ – Dorian Jun 12 '18 at 11:16
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Since you're dealing with ± 18 V, then you are going to need a voltage level shifter/translator somewhere. So why not just implement your functions with the 18 V rail? This way you will acquire the voltage shifting and your logic function at the same time.

But first, here's a schematic that shows you what you technically want.

enter image description here Link to simulation.

Important information regarding the gif above:

  • The left schematic is what you want to do. The right schematic is what you don't want to do. I'm trying to show you what your problem is and how you can solve it.
  • The two stacked green graphs are the voltage levels at the 1 nF capacitors at the gate of the mosfets.
  • The yellow graphs are the current through the wire that goes from the drain of the P-mos to the drain of the N-mos.
  • The 1 nF capacitors are not actual components, they are the parasitic gate capacitance of the mosfet which I have assumed to be 1 nF which, you will have to look in your datasheet for what you actually have.
  • The 10 Ω resistors in series with the diode is there because in reality you also have inductance everywhere, this means that you can overshoot the gate and destroy the transistor, with 10 Ω the current is limited so the overshoot minimizes.
  • The 330 Ω resistors in parallel with the diode and 10 Ω resistor are there to slowly ramp up the gate, while the other input takes the "short lane" with the diode. This will make sure that you get the delay you need.
  • The 10 Ω + diode + 330 Ω resistor makes the input impedance different compared the output impedance, so it will discharge faster than it charges, or charge faster than it discharges. The direction of the diode decides this.
  • The 22 Ω resistors on the right is to reduce the ringing due to the parasitic inductance that lurks around.

All in all, this would work great if you had a strong driver that goes from 0 V and 18 V. But I will assume that you do not have that, and give you a more general solution.


If you look on the left schematic above, you can notice some... important things. Such as from the top 1 nF to the bottom 1 nF the two 330 Ω resistors are in series. And the diode... you can technically replace them with npn and pnp and just connect their collector to VDD and ground respectively. BJT transistors are nice and all. But if you have some bad mosfets lying around, like some that has a \$R_{DS(on)}\$ of about 5-20 Ω. Then you can use them instead without any resistor. I will show you what I mean below.

enter image description here Link to simulation.

Again, the 1 nF capacitors are not actual components. They are the input capacitance of the mosfets. You should not add capacitance to the gates of the mosfets.

This time I am using very slow input (triangle wave) to show that regardless of how fast your input is switching, the output still won't short. Which the left schematic in the first gif will if you switch too slow. During the switching, the output of the half bridge is in high-impedance mode, meaning that it is floating. So here you technically have a guarantee that your output can't short. Which I believe is the essence of your question.

The parasitic inductance that is everywhere may cause ringing, so you should add a 5-22 Ω resistor between the 330 Ω resistor and the gate of the mosfets. Or if you are using mosfets with high \$R_{DS(on)}\$ then you won't need to add another resistor because the mosfet will be limiting the current => no/small oscillations. Ringing means that the two mosfets at the output stage will open/close because their gate is being drawn up/down at several MHz, this is not wanted, you will most certainly get shorts. If you want to see the effect, click here for a simulation. I've replaced vital wires with 100 nH which is not too impossible in the real world. The faster you switch, the worse the ringing becomes.


So of the two schematics in the gif closest above, the left one shows a simple voltage level shifter so you can drive your 18 V H-bridge with a ATMega2560, this is the one I believe you actually want. The right schematic is something you could use if you have a 18 V level shifter laying around.

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  • \$\begingroup\$ That's a horrible idea I think. At a minimum you need to add optocoupler. The consumers (trains) create a lot of noise on the rails with some feed back added in to ACK data packages. Shorts are also common when a train (car) jumps the rails. The required output signal is also +-18V. Meaning the power rail switches between +18V and -18V compared to the ground. A ground I don't want to share with the ATMega2560 and my connected laptop by the way. If I extrapolated your design to switching the full +-18V then I just end up building my own H-Bridge, which I already have premade. \$\endgroup\$ – Goswin von Brederlow Jun 12 '18 at 12:52
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I have implemented a non-overlap circuit discretely, and it is possible using gates and some form of delay. However, you're much better off using a dedicated half-bridge driver with built-in non-overlap delay (deadtime). That way you get good high-peak-current gate drive, deadtime and possibly fault detection. Here's just one example of a part: TPS51604 from TI. There are many other from IR, Maxim, Renesas/Intersil etc, depending on your specific requirements.

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    \$\begingroup\$ They might all be good solutions to buy. But I didn't ask for a shopping list. That doesn't teach anything. \$\endgroup\$ – Goswin von Brederlow Jun 12 '18 at 7:04
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    \$\begingroup\$ Your question was exactly "How do I make the H-bridge foolproof?" not "how do I learn about non-overlap circuitry?" You CAN use gates as per Andy aka, but how do you interface gates to drive a FET? 7400 series gates won't do 18V high-side drive, and once you add a (discrete? IC?) high side driver, you have another delay. Are you planning to use NFETs all around? Bootstrap or high-side supply? Or PFETs on top? How fast do you need to switch? What's your switching frequency? How much peak gate current do you need? My point is that the answer to foolproof is to use a gate driver IC. \$\endgroup\$ – John D Jun 12 '18 at 14:24
  • \$\begingroup\$ Also with discrete gates and a delay you have to be very careful about power-up and brown-out conditions, as well as temperature variations. So by all means give it a try if that's the way you want to go, but have some extra FETs on hand while you work to make it foolproof :) \$\endgroup\$ – John D Jun 12 '18 at 14:27
  • \$\begingroup\$ That's a good point about power-up and brown-out. I better add a pull-down resistor to the enable line so the default will be off. \$\endgroup\$ – Goswin von Brederlow Jun 14 '18 at 7:16
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My question now is: How do I make the H-bridge foolproof?

The lazy foolproof solution is to use integrated half bridge drivers. One IC that contains all the logic including the transistors. Popular example is the L293. You can also get half bridge gate drivers, like Si8274.
Some individual gate drivers also offer two input pins, On Semi has many.

If you're not looking for an integrated driver, then you can use the special motor control timers available on microcontrollers. For example, the Advanced Control Timer on STM32 chips have inverted complementary channels and dead-time insertion. ST RM0008 Rev 19 figure 86

When even these features are unavailable, you can use a discrete solutions as suggested by Andy Aka.

It is essential that these protections work, even if the chip is in reset state.

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