# Digital Circuit for Truth Table

I am trying to determine a circuit that will produce an output (W, X, Y, Z) given an input (A, B) based on the following truth table: What would be the simplest way to accomplish this? I was thinking about starting with a 2-4 decoder and add some digital gates, but would like to avoid too many parts. The point of this was to use 2 I/O pins instead of 4, but perhaps it is not worth it.

Thanks.

• Do you want a discrete logic solution (not, for example, how you would do this in an FPGA)? – The Photon Jun 11 '18 at 22:42
• Discrete logic is needed, yes. – Biff Jun 11 '18 at 22:51

## First simplifications

We notice that, whenever $A$ is set, $W$ is too, so the formula for $W$ will look something like $A +XXX$. Same goes for $B$ and $Z$. $B$ and $X$ too have this property

## Taking it from there

We further notice that, $W$ is linked to $A$ in an even stronger way (and same goes for $B$ and $X$). We have $$W = A$$ and $$X = B$$ $Z$ however, has a "special case". Even when $B$ isn't set, if $A$ isn't as well, $Z$ is set. So we need a signal that is $1$ if and only if $A = 0$ and $B = 0$. This is a NOR gate. So : $$Z = B + \overline{A + B}$$ $Y$ is set if and only if $A$ and $B$ are set. This is the definition of an AND gate. Thus : $$Y = A\cdot B$$

## Optimizing for less chips

From DeMorgan's law, we have $$\overline{A + B} \Rightarrow \overline{A} \cdot \overline{B}$$

Thus, as a recap, we see that : $$W = A$$ $$X = B$$ $$Y = A\cdot B$$ $$Z = B + \overline{A} \cdot \overline{B}$$ We need two AND gates, two NOT gates and an OR gate. As gates of similar types are often packaged by 2, 4 or 6, you should be able to get away with 3 packages.

• Z can be simplified further. – The Photon Jun 11 '18 at 22:58
• This process helps, thank you. With W and X I can wire it up in parallel with A and B, so that leaves me with an ANDN gate for Y and a NOR + OR combination for Z. – Biff Jun 11 '18 at 23:11
• I personally do not see how, at least in an motivated way (other than "just" building the truth table). I you'd like to edit my answer, I can make it a Community Wiki. – Sachiko.Shinozaki Jun 11 '18 at 23:18
• I didn't want to just hand the answer to OP (it's better for them if they have to think a bit) but, Z = B + ~A. If you're using DIP packages it may not make a difference, but if you're using SMT 1-gate packages, it saves a couple packages. – The Photon Jun 11 '18 at 23:23
• I understand your method, and will probably apply it in the future. I will maybe edit with a motivated explanation, if I find one. At worst, there will still be your comment. – Sachiko.Shinozaki Jun 11 '18 at 23:25

Think about each output as a separate problem, and you'll find it much easier.

W, X, and Y can be solved with 1 (or fewer, depending on your fan-out requirement) gate each. Once you see them, these solutions are trivial.

Z needs 2 gates.