[I will interpret your question as meaning design dram inside a custom ASIC chip]
DRAM is a specific foundry process (requiring HiK dielectrics and vertical features to maximise the pf/mm^2), not an option of a standard cmos process and foundry (as far as I know).
In a custom chip I was making DRAM seemed like it might be a good idea, as 90% of the data was only transitory, and there would be no refreshing required.
In the end I found two problems:
- Without the special (HiK, vertical) dram process, the dram cells are not especially small, as they need storage C.
- The driver blocks are large - equal in size to about 32k of SRAM, so only a much larger array (eg >256k) could make any sense.
There did exist a couple of dram block designs for use in standard cmos processes. Any chip designer can buy/use them. From memory one was a multi-process IP block, and another was a standard IP block for one of the major foundries 0.18um processes.
Neither turned out to be at all useful for the smallish ram I needed, and there would probably be a pretty limited number of times they could make sense, as for bigger spaces, using an external dram and co-packaging the chips would be better.