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UPDATE

I changed the top layer to try an other approach. What do you think ? (I didn't implement the vias yet, and didn't change the bottom layer, which is a full ground plane now)


I am designing my second ever PCB layout and I would like some feedbacks. The circuit is a basic step down converter using 12V as input, and outputing 3.3V. The maximal output current will not exceed 1 Amp.

Since I'm a newbie in PCB design, feel free to point out any mistake or tips to help me improve my designs.

Here is a link of the voltage regulator's datasheet, and pictures of the design.

Datasheet

Note : Just about the designators, ignore the ones that are badly placed (like the one on holes). It is just to help finding components on schematics, I will rearrange them later)

Schematic

New top layer

Bottom Layer

3D view

Thank you very much.

Fever

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  • \$\begingroup\$ Why the thick isolation? \$\endgroup\$ – winny Jun 12 '18 at 12:02
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    \$\begingroup\$ At a glance this looks like a boost converter schematic, because it is custom to draw the schematics from left to right. That is, if you are doing a buck converter you go from a high voltage to the left, to a lower voltage to the right. And yeah you probably copied it straight from TI... \$\endgroup\$ – Lundin Jun 12 '18 at 13:45
  • \$\begingroup\$ The trace on the Blue side of the board has two different via classes on the same trace. Looks weird and increases your board cost because of the extra drill change operation. Also it seems there are no fiducials (which is fine if this is a 1 off you're populating by hand). \$\endgroup\$ – Wossname Jun 12 '18 at 14:26
  • \$\begingroup\$ I will redo all the vias anyway, but thanks for pointing it out. About fiducials, I don't need them since I will hand solder the board. \$\endgroup\$ – Fever Jun 12 '18 at 14:46
  • \$\begingroup\$ Do the layout as in fig.36 in the datasheet. \$\endgroup\$ – Nick Alexeev Jun 12 '18 at 19:08
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The first two things that I look when I see a converter layout is hot nodes and hot loops (maybe they call it something else).

A hot node is a node in the schematic which the voltage of changes fast (lets say, more than 10x faster than the switching period). A hot loop is the loop in which current flow is effectively manipulated at the switching frequency. This is better explained by LT's (now Analog Devices) paper which I open up and take a look at when I feel lost. The first figure there is the following:

Hot loop

Source Here AN139 Another source here AN136

Unintuituve to many, once me included, the currents that are supplied to and drawn from the inductor and charges and discharges the capacitor, are effectively summed up. You can think that the blue and red loops alternate each period, but since in the path that they share together the current flows somewhat continuously, the loop that is formed by the subtraction of these loops exhibit the alternating current that effectively radiate. One aim is to make this loop as small as possible. This is a precaution against inductive coupling, which due to EMF, which effectively is a pure voltage source, which adding capacitors to the design afterwards does not mitigate. Make the loop that goes through the closest and smallest package input voltage capacitor to the converter input voltage lead, the converter ground lead to the ground terminal of the same capacitors as small as possible. In your case, this seems perfect to me.

The other concern is the capacitive (electric) noise. The source is large areas which the voltage changes fast. In a buck converter, this is the node that is connects the converter to the inductor. In most cases the intuition to lay thick traces out for high current lines is misleading here. (Unless the current is so high that your trace resistance becomes an issue, which is not the case most of the time.) Make this node as small as possible. In your case, it seems good, but I cannot say much unless I see the actual dimensions. It can get a bit smaller, I think, but no biggie.

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This is a nice, tight SMPS design. The suggestions below may be considered partly my own opinion, but it's an educated opinion.

  1. As already mentioned, more vias are usually better. In particular, ground vias near the input caps and the IC ground would be good.
  2. If it were me, I might swap the output caps with the sense resistors to lessen the distance the return current has to flow to get to the chip and input cap ground connections. A continuous ground path for this loop on the top would be great, but I'd still via both the input and output caps firmly to the bottom ground plane as well.
  3. Most importantly, your switching waveform and return currents both have to cross the ground plane discontinuity caused by the connection between R1 and the IC. A continuous ground plane keeps your current loops small. It may seem counterintuitive, but you'd probably be better off routing that (DC) signal the long way around, keeping a continuous ground plane under the current loops pointed out so clearly and artistically by @mehmet.ali.anil. In an excess of caution, I'd probably move R1 closer to the chip so the long runner would be a lower impedance node (+12V).

Okay, I know some Altium purists are going to point out that the bottom isn't technically a plane, but a polygon, but you see what I mean. Nice work!

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You ought to have the chip identified on the schematic.

You have an acute angle between two tracks.

You don't seem to have the recommended vias between the top and bottom of the board around the chip connections.

Provided you have followed the layout guidelines you should be OK.

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