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I'll be using a 12MHz crystal, CL=20pF on an NXP chip. Currently choosing between lower ESR (60ohms vs 100ohms) or lower stability (50ppm vs 10ppm). Which spec is more important? Should I choose a lower ESR @50ppm or higher ESR @10ppm?

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  • \$\begingroup\$ With my limited experience, I'd say stability is the more important parameter. \$\endgroup\$ – Hearth Jun 12 '18 at 14:22
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    \$\begingroup\$ How stable do you need it to be? You might have to factor in aging, temperature, etc. \$\endgroup\$ – Cristobol Polychronopolis Jun 12 '18 at 14:24
  • \$\begingroup\$ is that Tolerance or Temperature Stability? I think you mean Tolerance at room temp. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 12 '18 at 14:32
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What "stability" means in this context is a bound on the effects of temperature. For example, the manufacturer may guarantee that the frequency will not change more than 10ppm over the range of -10 to +60°C. It is distinct from initial tolerance.

ESR has an effect on the pullability of the crystal and the power dissipation and probably jitter.

If you have too much power dissipation you can cause the crystal to drift over time just from that cause.

Personally I would be inclined to pick the one with lower ESR unless precise timing was of some great importance in the application. Or maybe the one with high availability, pedigreed supplier and lower price.

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There are several sources of error in XO crystal oscillators. ESR is not one of them, but for series resonant oscillators which resonate at a slightly offset frequency, and Q dependent VCXO tuning range ESR is very important. So consider all below.

  • Tolerance error at 25'C (ppm) due to factory sorting and smaller tolerance angle cuts on crystal
  • Temperature stability error over defined range can make a big difference as the curve for AT XTals is a 3rd order characteristics depending on Xtal angle cut. One can choose a narrow range and get a lower slope temp error curve near room temp but wider offset range at extremes like -20~50'C, -30~60'C or -40~70'C depending on your environment.
  • aging error; this depends on quality of synthetic purified SiO2 (quartz) crystal from electrode migration of impurities and package seal. It can also be dependent on drive level in uW where lower is better and lower temperature. But often spec'd as 5ppm in 1st year at 25'C and may reduce per year after this
  • vibration and shock error , wire bond stress to crystal can offset the frequency and they are prone to early failure if Xtals are dropped on the floor. This can shift as much as temperature but depends on high level of vibration.

  • When I had a database of stock part numbers, my description would include xx MHz 25/50/5 -40~70'C (for tol./stab/age) , package size and load pF

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It completely depends on your application. What are the specs of the NXP chip? How much -R does it have, and how much accuracy do you need?

ESR affects how quickly and easily the crystal starts. Basically, how hard it needs to get "hit" with current to start oscillating. Low ESR means more reliable startup of the crystal across PVT.

If the NXP chip has substantial -R, then you don't need a lower ESR crystal. In fact, the extra power is just going to cause faster aging of the crystal. The rule of thumb is that -R should be 3x the ESR.

If your application needs better accuracy, then obviously you'll want to use the low ppm crystal (assuming that you can guarantee that it will start up across conditions). Tony Steward older than dirt has already covered accuracy in his answer.

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