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Following the failure of my first board design, I designed the following STM32F103C8T6 board. I only routed the fundamental parts of the board(MCU,caps, crystal, regulator etc.)

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This is a 2-layer board with top layer being GND+signal and bottom layer being VDD+signal. Caps and resistors are all 0805 package.

My question here is, is there anything wrong with this design? Are there any flaws? I placed some of the decoupling caps under the board, otherwise I found it impossible to route some tracks. I'd also be glad to hear general opinions about the design.

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    \$\begingroup\$ I won’t do a complete DFM,DFT on this design , but you can read about how to lower costs with no hand stuffed parts, add test points , use microvias instead (many) and have self test code after Power on Reset with indicator codes for fault detection and isolation. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 12 '18 at 17:36
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    \$\begingroup\$ It appears to be battery powered, you're going to be wasting a lot of your energy with the linear regulator, a buck converter might be better. \$\endgroup\$ – Colin Jun 12 '18 at 19:58
  • \$\begingroup\$ @Colin__s I added a LM2596 buck converter to the board. This will efficiently drop the voltage to 5V. The linear regulator is going to drop that 5V to 3.3V. \$\endgroup\$ – zeke Jun 14 '18 at 18:42
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I recommend a pull-up resistor from NRST to VDD and a feritte bead + 100nF + 1uF bypass capacitor to decouble VDDA from VDD when you use your ADC. Further, you should implement a jumper for your BOOT0 pin, such that you can choose between VDD and GND for changing the boot configuration.

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For your PCB design, I recommend to use more vias to connect the top and the bottom GND layer. Additionally, you should add some mounting holes. You can also put all your bypass capacitor under the board, normally this way you have the least distance from VDD to GND and your other GPIOs have more space.

Edit: I see that you have a bottom VDD Layer, you don't need this on a 2 layer pcb. Just use one GND layer at the bottom and separate traces for VDD only where needed.

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  • \$\begingroup\$ VDDA already has a 100nF + 1uF and that's what the datasheet suggests. Do I really need a ferrite and two more caps? By the way, top layer is GND, not VDD. \$\endgroup\$ – zeke Jun 12 '18 at 17:33
  • \$\begingroup\$ You don't need to add two more bypass capacitors, but you go normally better when you use a ferrite bead followed by your 100nF + 1uF directly at your VDDA pin if you use your ADC to reduce noise. \$\endgroup\$ – HansPeterLoft Jun 12 '18 at 17:36
  • \$\begingroup\$ I don't plan to use ADC so I hope I can get away without a ferrite. \$\endgroup\$ – zeke Jun 12 '18 at 17:37
  • \$\begingroup\$ Your advice about the NRST is wrong. NRST should be connected to GND via the 100n capacitor as recomended by the STM. It is not an AVR uC!!!!\ \$\endgroup\$ – P__J__ Jun 14 '18 at 14:48
  • \$\begingroup\$ @PeterJ_01 Would it cause any problems though? \$\endgroup\$ – zeke Jun 14 '18 at 15:54

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