I'm designing a board using the ATtiny84A which uses a USI (Universal Serial Interface), and as such there is no dedicated I2C and SPI peripheral.
I have gotten I2C to work and tested it by communicating with a 24AA02UID EEPROM.
I have gotten Slave SPI to work and have tested it by returning requested data to a master.
My question is: if the ATtiny has no control over if/when the master decides to start an SPI transaction, is it possible to use these same USI pins to query the EEPROM over i2c?
I'm guessing that allowing the external SPI master to use the i2c pins that are attached to the EEPROM willy-nilly is going to cause strange data to appear on the EEPROM if/when the master happens to send a byte corresponding to the i2c address of the EEPROM chip, followed by other random data.
Or, am I worrying too much? I was hoping that the SPI signals would be disregarded by the EEPROM due to improper i2c protocol formatting.
The problem of the external SPI master taking control of the lines during a i2c communication sequence is troubling, however.
Is the best solution to use a tristate buffer that my ATtiny84a can toggle to cut off the external SPI master from the lines in question whenever it wants to read/write to the EEPROM?
It would seem that the cheapest and easiest and most awesomest solution is to simply use a different ATtiny chip. I think I will go with the ATtiny88 which has a dedicated TWI and SPI port (on separate pins):