As an assignment for the HDL course I'm taking, I've to design an FIR Filter. The module consists of two a small combinational circuit which can be used to reset the module, another combinational part which handles the convolutional multiplication and therefore, is considerably bigger and finally a bunch of registers all using the same clock pulse signal.
The odd thing is after synthesizing and implementing, the software reports that it can operate at a maximum clock rate of around 600MHz! Apparently, the latency of the combinational circuits in total is about 27 nanoseconds but the minimum clock period is 1.5 nanoseconds.
So to generalize the question, consider the following module:
S is considerably larger than
T should the minimum clock period be as large as
S or does it depend on
T? Or should it be larger than