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As an assignment for the HDL course I'm taking, I've to design an FIR Filter. The module consists of two a small combinational circuit which can be used to reset the module, another combinational part which handles the convolutional multiplication and therefore, is considerably bigger and finally a bunch of registers all using the same clock pulse signal.

The odd thing is after synthesizing and implementing, the software reports that it can operate at a maximum clock rate of around 600MHz! Apparently, the latency of the combinational circuits in total is about 27 nanoseconds but the minimum clock period is 1.5 nanoseconds.

So to generalize the question, consider the following module:

enter image description here

If S is considerably larger than T should the minimum clock period be as large as S or does it depend on T? Or should it be larger than S+T?

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  • \$\begingroup\$ By the way, the module was implemented on XC6SLX9 with speed grade -3. \$\endgroup\$ – Mohammed Farahmand Jun 13 '18 at 12:40
  • \$\begingroup\$ There are no signal paths that connect from a register output, through some logic, back to a register input? If there are, you should change your diagram to make that clear. \$\endgroup\$ – The Photon Jun 13 '18 at 14:34
  • \$\begingroup\$ Nope, there aren't. That's why I haven't drawn any. \$\endgroup\$ – Mohammed Farahmand Jun 13 '18 at 16:14
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    \$\begingroup\$ FWIW.... Rule-of-thumb: Always register your outputs (and inputs if possible) if you can afford the latency. And, if you can't afford the latency because of the given requirement, push back on the system designers until they have confirmed that requirement has no room to change. \$\endgroup\$ – CapnJJ Jun 13 '18 at 18:56
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Since you have synchronous registers between the combinatorial blocks, the minimum time is the larger of the minimum time for each block.

The S block will process the data generated by the T block during the last clock period, while the S block processes the next data items.

So you can increase \$f_{max}\$ by shrinking your combinatorial blocks and putting registers in between, but the results will arrive on a later clock cycle then.

It is quite possible that the synthesis identified the multipliers in your design and mapped them to dedicated multiplier blocks, reducing the settling time for S significantly.

It is also possible that you have an error in your design that allows the compiler to optimize out functionality, e.g. by not routing output signals to pins you are allowing the compiler to remove the entire design as it has no externally visible effects.

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  • \$\begingroup\$ No, I actually checked the schematic for the final result and the multiplications and additions are all done without flip-flops in between. \$\endgroup\$ – Mohammed Farahmand Jun 13 '18 at 16:17
  • \$\begingroup\$ @MohammedFarahmand, the synchronous registers from your diagram should show up as flip-flops. The XC6SLX9 has 16 DSP48A1 slices, each of these has an 18×18 multiplier element, so if you have fewer than 16 multiplications per cycle, it is quite possible that all of these have been mapped to DSP blocks, which should give you a good \$f_{max}\$. \$\endgroup\$ – Simon Richter Jun 13 '18 at 16:42
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I suspect that you have failed to add constraints for the input setup time and the output delay. These must be added to get accurate timing estimates. Also, you probably need to add an additional set of registers at the input pins and another at the output pins. Once you add these registers the minimum estimated clock period should be equal to the largest propagation delay through the combinational logic plus the FF setup time plus the FF clock-to-Q delay plus wiring delay.

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  • \$\begingroup\$ Thanks for your answer but right now I'm not concerned with how to get the right frequency out of the software. I wish to know which of the combinational circuits defines the minimum clock period? Is it the one before the flip-flops or after them? Does it even matter or does it all depend on the amount of the delays each combinational part has? \$\endgroup\$ – Mohammed Farahmand Jun 13 '18 at 12:55
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    \$\begingroup\$ You can calculate a clock period only if you have at least two sets of registers that use a common clock and have logic between them. Otherwise, you need to use constraints to describe the behavior of external registers. \$\endgroup\$ – Dave Tweed Jun 13 '18 at 13:24
  • \$\begingroup\$ "but right now I'm not concerned with how to get the right frequency out of the software." I don't understand your 'but' The only way to get the right frequency is to do what @MohammedFarahmand told you: you have to set input and output constraints. The alternative is, as he says, to add output registers, in which case the SW has two points to do the delay calculations on. \$\endgroup\$ – Oldfart Jun 13 '18 at 15:03
  • \$\begingroup\$ I meant that I'm not concerned with the coding styles I've to follow for the software to calculate the clock correctly. I wanna know if you could find the minimum clock by hand if you know the propagation delays of the combinational circuits. \$\endgroup\$ – Mohammed Farahmand Jun 13 '18 at 16:16
  • \$\begingroup\$ And here's what ISE reported in case it helps: Timing Summary: --------------- Speed Grade: -3 Minimum period: 1.506ns (Maximum Frequency: 663.967MHz) Minimum input arrival time before clock: 4.508ns Maximum output required time after clock: 27.076ns Maximum combinational path delay: No path found \$\endgroup\$ – Mohammed Farahmand Jun 13 '18 at 16:21
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It depends on context we don't have.

If you expect to cascade these modules, then the clock period is the sum of delays S and T.

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I suspect your FIR, max f_BW << f (clk)< 1/t(S) so f(clk) is independent of S and only dependent on t(T). Often multi-phase clocks are used, such as in DDR to reduce the latency even more and resync intermediate async circuit latency.

All external clocked registers must be included in analysis. So the general rule is simple Async latency followed by Sync clock where latency+ setup+hold time must meet the clock timing. This is then cascaded as many times as needed with single or multiphase clocks.

Also all buffered memory (FF) add latency.

Therefore you choose the tradeoffs between how many multi-phase clocks and async metastable races depends on your max speed requirements and async latency to optimize cost/value of latency.

e.g. hence the generation of DDR5 for GPU's offers the fastest speed at optimal costs and next Samsung's DDR6 DRAM https://www.anandtech.com/show/12338/samsung-starts-mass-production-of-gddr6-memory

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