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I followed a schematic and mocked up a Latching toggle switch with NAND gates. (see picture below for what I followed)

original schematic

(Source)

I have mocked it up onto a breadboard. Using the exact same values of resistors and caps. The NAND gate that I used was a CD4011BE.

Datasheet is ( http://www.ti.com/lit/ds/symlink/cd4012b.pdf )

I had it jumpered to the actual PCB and using the actual button I want to use in the change of design. (adding this circuit to the PCB on the next rev) and it worked great.

Now that the change has been made to the PCB and we have some in to test, it does not work.

My schematic is below.

my schematic

I am actually driving an inverter that is driving a enable line. When the enable line is high my device is on and when it is low the device is off. This latching NAND circuit won't actually come on, which means my device never turns off.

Also it is all being powered (inverter, NAND, other circuits) from a lipo battery. The data sheet for the NAND gate is http://www.ti.com/lit/ds/symlink/sn74lvc2g38.pdf

The voltage as I have been testing is around 3.78V DC as expected from the lipo. Between R9 and R10 it's only showing 1V DC when the button is not pressed and between R10 and C11 it's showing about 0.87V DC.

I suspect that maybe the NAND gate I'm using is not able to work for this for some reason, but looking through the data sheet I couldn't find a reason it wouldn't. I have verified that the PCB layout is correct and in my schematic A1 and B1 is one gate and A2 and B2 is the other gate.

Any help would be greatly appreciated.

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The datasheet says that the NAND gate you are using has open drain outputs. The breadboard version had standard totem pole outputs. I'm not sure how your circuit can work with open drain outputs.

The SN74LVC2G00 is a standard output version with the same pinout that should work better.

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  • \$\begingroup\$ So that should be the issue then im guessing. Open drain outputs. You think the one you suggested will work? \$\endgroup\$ – Rob Jun 13 '18 at 15:36
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    \$\begingroup\$ Rob, I hope crj11 won't mind me saying this but you seem to have accepted the first answer to appear while still unsure (in your comment) about its accuracy. We normally recommend you give at least one rotation of the planet so that the whole of humanity gets a chance to answer. While you might not get a better answer you will find that it encourages others to give answers perhaps with a different angle or some new information for you. You are able to un-accept if you wish and then re-accept later if this is still the best answer. \$\endgroup\$ – Transistor Jun 13 '18 at 16:40
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    \$\begingroup\$ @Transistor36, I don't mind \$\endgroup\$ – crj11 Jun 13 '18 at 16:41
  • \$\begingroup\$ @Rob, Since the new gate is also CMOS with low input leakage, it should work the same as the CD4011 version. The new outputs will change a lot faster with modern 24ma CMOS logic, so if the circuit is driving a long net and it is not terminated, the reflection of the edges could be a problem. This depends on your logic at the receiving end. \$\endgroup\$ – crj11 Jun 13 '18 at 16:50

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