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I'm trying to design a simple SRAM board (using a cypress Cy7c1011cv33) to connect to my lattice machox3 starter kit's pin connectors. But I have some design questions, after reading their "SRAM Board Design Guidelines". The guideline says "PCB should be designed to inductances as low as possible", but how high can the inductance be? also is it advisable to connect two SRAMs' address and data pins together? I ask because then the vias will be longer, which goes back to my question about inductance. I made a simple board with one sram ic, but I calculated (by hand not with kicad) its inductance to be 51nH and have no idea if thats okay or not.

I plan on using the SRAM near its full speed (100MHz) and I'm using kicad to design the board (only because I can keep the track length constant without having to pay a small fortune). This is the first time I'm trying to design something that works this fast I usually stick to PICs MCUs and analog circuits so any help is appreciated.

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  • \$\begingroup\$ You have the ability to simulate your design? The guideline you quoted went on to give a bulleted list of things to consider to minimize inductance. I don't think there is a "magic number", but some of the PCB (or analog otherwise) folks might be able to tell you what they think about your result(s) after you try some different layouts. Also, in my experience of boards designed for my ASICs/FPGAs, if you have several discrete memories to make up "one large" memory, it is common practice to combine the data/address traces from the discrete parts such that they are all one bus at the IC. \$\endgroup\$ – CapnJJ Jun 13 '18 at 19:02
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The "SRAM Board Design Guidlines" that you reference mostly discusses minimizing the inductance of the power supply pins and decoupling capacitors. To minimize the inductance, it is best to use a PC board with power and ground plane and to have the leads from the power pins to the associated bypass capacitor be as short as physically possible. There are many online sources of low cost 4 layer PC boards.

For the signal lines, the design guide does discuss termination. Depending on how long the traces from the MACHXO3 to the SRAM are, you may need to use termination to eliminate the noise caused by reflections. A rule of thumb is that you don't need to worry about termination if the length of your traces are at least 10X the edge rate of your signals. A PCB trace is typically ~150ps/inch.

Another reason to use a four layer board is that routing traces over the power/ground planes gives better transmission line characteristics than can be achieved with a two layer board, especially for wide busses.

Paralleling two SRAMs should be OK as long as you keep the connections between the chips short.

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It means you route everything (all of the fast signals like address and data lines) on the top layer and for the signals you want running at 100MHz you run them as short as possible. If your trying to connect an SRAM off board, your probably not going to be able to do that without impedance control of the lines, and connectors.

The pic below shows an FPGA with an SRAM with most of the traces routed on the top layer. If you don't do this, then when it doesn't work you have to go through each signal and measure the delay and make sure its within bounds of the datasheet. That doesn't sound like much fun, so I follow the guidelines and overdesign.

enter image description here

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