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Below they're connecting the feedback voltage FB to positive pin of op amp. Isn't this positive feedback ? Because, when the output voltage increases, the feedback voltage increases, which then increases the op amp output.

But my textbook claims that the output voltage is stable because of the heavy negative feedback. I'm not able to see negative feedback here. What am I missing ?

enter image description here

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    \$\begingroup\$ It's a P-MOS transistor. The higher the gate voltage, the more it turns off. Increasing feedback -> increasing op-amp output -> decreasing current. \$\endgroup\$ Commented Jun 14, 2018 at 3:53
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    \$\begingroup\$ Yes - it is counter-intuitive to a normal feedback loop, because it is driving a P-Channel MOSFET. The higher the feedback voltage is away from the reference voltage (i.e. the higher the error), the higher you want to drive the P-FET. \$\endgroup\$
    – DSWG
    Commented Jun 14, 2018 at 3:54
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    \$\begingroup\$ Wow! so that PMOS is providing 180 degree phase shift to give negative feedback! I completely missed that! Thank you so much :) \$\endgroup\$
    – AgentS
    Commented Jun 14, 2018 at 3:56
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    \$\begingroup\$ Now that you have that part, build one and see if it oscillates. \$\endgroup\$
    – jonk
    Commented Jun 14, 2018 at 4:00
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    \$\begingroup\$ @rsadhvika a general zener is okay, but you can get diodes designed to be reference voltages (i.e. more accuracy, temperature compensated, etc.). Just google "1V voltage reference" or something, as an example. \$\endgroup\$
    – DSWG
    Commented Jun 14, 2018 at 4:16

2 Answers 2

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It's a P-MOS transistor. The higher the gate voltage, the more it turns off.

As the feedback voltage increases, the op-amp increases the gate voltage, which decreases the current.

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There is 180 phase shift across gate to drain. So, for a PMOS: feedback should be connected to a + ve terminal for a NMOS: feedback should be connected to a - ve terminal

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