# RC differentiator circuit explaination This is the circuit of a basic RC differentiator, with the input/output voltage waveforms.

1. First of all, I don't understand why there is decrease in the output voltage (discharging of charge from capacitor) as long as the supply is still on.
2. Secondly, I don't get why the voltage across the resistor falls to a negative level.

I know it is a simple question but please help me to understand this basic circuit - thanks.

• +1, nice diagram. Also, your question may seem simple, but it's not trivial! Aug 15, 2012 at 12:43

Long story short: For a low-to-high transition of your input signal, your capacitor isn't discharged, it is charged, and it remains charged until the high-to-low transition occurs.

Nevertheless, here's the long story:

We take the freedom to start with changed positions of R and C; note that Iin = IC = IR, so we really are allowed to do this (KCL). This is the picture you usually see for a capacitor being charged through a resistor, so it may be worth the effort: We can see how C is charged according to the RC time constant and according to the magnitude of the input voltage step from 0 V to Vin. Also, we can see how the voltage remaining across the resistor on top of the capacitor becomes less the more we charge the capacitor: VR = Vin - VC. This almost answers your first question about the decrease in output voltage already; we just have to turn this configuration upside down again.

Here's your original circuit again, with some symbols we will need for the explanation, the assumption that we have no load, and the equations showing Vout  for C on top and R at the bottom. We can imagine how the upper plate of C remains at Vin, the lower plate becomes charged towards 0 V, and finally, there is no voltage left across the resistor, between the lower plate and 0 V.

This finally answers the first part of your question (Why is C discharged?) - It is not discharged, it really is charged; we're just not looking at the upper plate, but at the lower plate connected to the resistor, gradually being pulled low through R.

Now, let's remember that the output voltage is equal to the voltage across the resistor. Vout = VR = R × IR, and again, assuming that Iout = 0 (negligible load), Vout = R × IC. In other words, the output voltage is proportional to the charging current of the capacitor, scaled by the value of the resistor R.

A low-to-high step of the input signal will thus create a positive spike across R, as we have already calculated. When we reverse everything, we see how a high-to-low step will create a negative spike because the current through C is flowing in the opposite direction of the arrow we have used for IC - which answers the second part of your question ("Why do we get a negative spike at the output?").

If you like (and I think it's fun!), you can draw some more pictures and calculate the high-to-low event for yourself.

edit
The negative voltage is a bit unexpected if you know that there isn't a negative supply. But it makes sense when we look at the voltage across the capacitor. When power is first applied the voltage on both sides of the capacitor is zero. We start the square wave, and the input goes to 5 V. Capacitors are reluctant to have fast voltage changes across them. You'll have to supply a lot of current to charge them fast. But the resistor doesn't allow this, so what initially happens is that the right side of the capacitor just follows the input; it also jumps to +5 V, and then slowly gets charged through the resistor. (Note that charging here means decreasing the voltage, since the voltage at the input is positive.)

When the input goes to zero something similar happens. Again the output will follow the input because the voltage won't change that fast. But the input was at 5 V and the output at 0 V. So when the input dives to zero, and the capacitor will maintain the 5 V across it the output has to go to - 5 V. I've added a third curve to your drawing. The top one is input, the middle one is output, and the bottom one is the difference between those, i.e. the voltage across the capacitor. You can see that it follows the familiar charge-discharge pattern, without fast voltage changes.
end of edit

The lowering voltage(*) is due to the resistor. It will exponentially draw the output voltage down at a rate determined by the time constant RC. After 1 RC time the voltage will have dropped to 37 % (1/e), after about 5 RC times to 1 % (rule of thumb).

Here's another way to look at it:
The negative edges are caused by the edges' high frequency. An edge has a wide spectrum, the steeper the edge the wider the spectrum. Unlike lower frequencies those high frequencies will pass through the capacitor almost unattenuated. So if the input shows a negative edge going from 5 V to 0 V you'll have a 5 V negative-going edge at the output. If the level is near zero at that time the voltage will go to -5 V. If the RC time constant would be higher the voltage will not have drooped as much, and the negative pulse may go for instance from +2 V to -3 V.

(*) I misused the word "discharge" here, which, as zebonaut rightly pointed out, is wrong. What you're doing is charging the capacitor. The input will be at +5 V and so will the output for a moment, since there's no change on the capacitor. As the output voltage decreases the voltage across the capacitor increases, which means it gets charged, not discharged.

• But my point is, capacitor must not discharge till signal is 1(5v), as its can recover discharged charges from power supply and voltage across the resistor(output voltage) will remain same as highest possible voltage. Aug 15, 2012 at 11:11
• @nishu - your (accurate) drawing shows that this isn't true. The capacitor and resistor form a voltage divider where low frequencies have a high attenuation because the cap's impedance is then much higher than the resistor's. So low frequencies get filtered out, and DC completely disappears. Apply a step voltage to the input, and the output will see the step's high frequencies, but after a short time (5 RC) the output becomes zero. That's because the input has only DC, which gets blocked, so there's nothing at the output. Aug 15, 2012 at 11:25
• @stevenvh - I agree to the second part of your answer, but I am not sure the first part is right. If you want to discharge a capacitor using a resistor, you must connect the resistor in parallel to the capacitor. Here, it is a series connection, so at least for IN going from low to high, I suggest an explanation using a charging event. While the input remains steady at high, no discharging takes place. Aug 15, 2012 at 13:14
• @zebonaut - right you are! I'll fix it. Thanks for the feedback. Aug 15, 2012 at 13:16

The first step to understanding this, is to understand the nature of "voltage". To do this, you must understand ("grok") Ohm's law.

Ohm's law tells us that the output voltage, which appears across the resistor, is determined by the current through the resistor. When the input voltage first rises, current flows through the capacitor and through the resistor.

Then the capacitor charges up. When it's charged, current stops flowing through it. It also stops flowing through the resistor. Now the voltage across the resistor is zero.

Understand this, and you may be able to work out the rest.

Resistor and capacitor are connected in series. In order to understand, you must understand how does current flows through it. It is obvious that for steady DC input, current must be zero after some time, since capacitor is like open circuit for DC excitation. Current is largest at the moment when input voltage is applied on RC circuit, and later it exponentially drops. Since output is product of constant resistance and exponentially dropping current, this is the reason why output voltage dropping down while input voltage is still there.

Secondly, when you make sudden change at the input, this change immediately affects another plate of the capacitor, since you can't suddenly change voltage across capacitor plates (you would require infinite current for that). Smaller the resistor, RC circuit is closer to perfect differentiator. You can simulate this on

http://www.cirvirlab.com/simulation/r-c_circuit_differentiator_online.php

initialially both sizes of the capacitor have the same voltage (vdiff = 0), doesn't matter if vin (side A of cap) is 0 or 5v or anything, vout (side B of cap) will be the same. So when square wave shoots to 5v at time0 vout also shoots to 5v. as time passes cap is being charged so side b of cap (or vout) becomes 0v. Now vdiff across cap is 5v. when square wave drops to 0v, since vdiff across cap must maintain 5v, THIS causes vout (or side b of cap to read -5v. So the key is vdiff across cap, got it? good