# why do they use NULL in VHDL code

From times to times I see different code examples that have " ... else Null" strings in if-statements and it's something I don't get. I've learned and I stick to the idea that the best way to model nothing is write no code. But is there any difference in these aproaches? if not then why do people write this "else null"?

• Are you talking specifically about if-then-else structures or also switch cases with when others => null; ? – DonFusili Jun 14 '18 at 11:30
• Please provide one or more concrete code examples you would like explained. Null can be used in several different ways in VHDL. – Lincoln Jun 14 '18 at 12:55
• Basically QA. else null; means I didn't just forget this bit, there really is nothing to do here;. As VHDL tends to be used in high integrity applications and some customers insist on critically reviewing every line of code, it really is the simplest and cheapest way to do the job. – Brian Drummond Jun 14 '18 at 12:56
• Apart from the good answer about QA, it may be to be able to place a breakpoint on that line in a VHDL simulator. – TEMLIB Jun 14 '18 at 20:48
• (A null statement can be labelled, see the answer referencing 10.14 in the standard. However neither breakpoints nor simulator user interactivity are defined in IEEE Std 1076-2008.) – user8352 Jun 15 '18 at 0:23