Replying as one nonEE who did his share of circuits to another nonEE...
First of all you have a clean schematic and a clean layout, so chances are things will just work as they are already. This is the benefit of overthinking the design in the right way.
Now, for the questions per-se:
Are you overthinking it?
That depends what is your definition of "ultra-precise" is and how good your design is without overthinking.
A simple calculation with numbers from the sensor and ADC tells us that $$ \frac{1 kPa}{46mV} * \frac{2*5V}{2^{15}} \approx 2.3 \frac{Pa}{LSB}$$ your highest achievable theoretical precision is 2.3 Pascal per each bit of output. I assume that's way too accurate and we don't really need that.
Now we go and look at the noise from the sensor. Figure 1 shows that we have little less than 20mV peak-to-peak of noise, witch translates to about 0.4 kPa. Lets assume this is too much of an error for you and we need to remove it.
This is broadband noise that starts at 500 Hz and goes well beyond Nyquist threhold. From the plot at p. 19 of the ADC datasheet you can see that oversampling will not really help with this noise. But a simple RC filter will bring the noise down to several mV. Alas! You have a filter, just the wrong one. If you look at the application note you will the see the recommended values of the filter (650 Ohm, 0.33 uF). And since the ADC datasheet clearly states we do not need a buffer before it we can just use the simple RC filter you already got.
But here comes a problem. The sensors output is ratiometric. That is, it depends on the power supply voltage. (Take notice that all the reference voltages at the sensors' datasheet are given at a supply voltage of 5.1 V.) But the ADC has an internal, stable, reference voltage (that adds its own DC bias to your measurement). So now we go and look at your power.
The combined maximum current consumption of the sensor and ADC is \$ 6 * 0.1 mA + 27 mA \approx 28 mA \$ and under those condition up to about 60dB of input noise from DC to 10kHz is filtered. So we can assume that under normal conditions the power supply noise will be much less than 1mV.
Do I really need ground separation?
At this point we can say that if you only need an accuracy of 0.5 kPa you can even remove the RC filters and not worry about a thing.
But if you need something better than this is the time to start thinking about things such as ground and power separation.
Do I really...? Should I....? What about power...?
To answer all your other questions, lets assume you do need ground separation.
First of all, in your current design, your ground is not separated. By using a single tie point in the layout you might have avoided some nasty ground loops (that act as antenna and pick up whatever noise there is), but you could have achieved simpler (and usually better) results if you'd just flood fill the entire bottom side with ground.
In case of a flood fill with no islands and no narrow bridges everything is good. Also, if you must do a fill at the bottom layer it is usually better if it is the ground in case the insulation scrapes off and the conductor touches whatever is below it. Since there is usually some chassis, and chassis are usually at ground potential... you get the picture.
This is not always good since it creates a parasitic capacitance between the ground and other traces. Sometimes it can be used for good, sometimes its a problem.
This is actually why I personally never do less than 4 layers on projects where I can afford the extra cost, because in that case the inner layers become grounds and powers and there are almost no problems with ground loops.
Now, if you want to do a proper ground separation then you need to have a net with a name different to "GND" in your schematic. I usually use "DGND" and "AGND", other people call it other things. Then you find out what frequencies you want to filter so they won't reach the analog ground (this is usually the clock frequency of your digital stuff), you you build an RLC (not RC) filter and connect the grounds using the induction of the filter, not the capacitance.
For this to have any meaning each ground zone/area must have its own, filtered, power supply(LDO).
Some remarks on the current design
To get the best layout look at the datasheets for both the ADC and the LDO. Towards the end they have layout recommendations with reasoning. It's really helpful to learn from that. Their layout solves many problems you might not even encounter but it, usually, will not create new one without someone warning you about it.
BTW, you're wasting half the range of your ADC because its bipolar and your design is not.
Many designs ago, on a PCB far away...
If we assume that you do not need something extreme accuracy-wise, I would just take a Cypress PSoC5 developement board. It costs about $10, and it has everything you need for this project on a single chip. Including a USB connection to the PC with drivers. Oh, and the multi-channel ADC project is just one of the existing demo projects for the CPU.
Am I over-answering this? Even if so I Hope I could help.
