0
\$\begingroup\$

I have been trying to read about I2C pullups such that I can select an appropriate pullup resistor for an EEPROM (24LC02B-I/P) which I want to use as serial ROM to drive some 7-segment displays.

Despite the advice in this 'AddOhms' video I still am curious about how you actually calculate a pullup and a caulcated pullup range, but this TI document baffles me totally in section 2. Below are some specific questions:

  1. Why does Rp(min) take an output low voltage from Vcc?

  2. It talks of bus capacitance: the only reference I can find on the datasheet of the EEPROM is to pin capacitance (10 picofarads)- is this one and the same?

  3. How comes T(r) is the rise time between Vol and not V = 0, or some median between Vol and V = 0? I was under the impression Vol was a determined V output maximum but necessarily the actual value.
  4. How comes the calculations deal with output low/high for strong pullup and input low/high for weak pullup?

Sorry if these questions seem diverse and broad, I am just struggling with the concept generally and getting a bit frustrated with it

\$\endgroup\$
1
\$\begingroup\$

In I2C protocol, the device operate in open collector or open drain mode. The devices (both microcontroller and the EEPROM) can drive the pins to logic zero (strong zero, assume as if they literally take the lines and short it to ground).

The logic one is merely achieved by the pull ups which are provided externally. Pull up resistor is in kilo ohms. (We will seethe values in a moment). There will be parasitic capacitance on the bus due to multiple I2C devices connected, PCB stray capacitance etc..

When signal is going high, the current has to flow from VCC through the pull up resistor and to the IC pins. So, the RC time constant kicks in.. It makes the rise of the signal sloppy. Example, if capacitance is 100pF and pull up is 10kohms.. Rise time will be five times R*C. Here, it will be 5us.

The fall time will not b an issue because, it will be almost instant.. From the IC pins to ground.. There is no resistors in the path to delay.

Question 2

It talks of bus capacitance: the only reference I can find on the datasheet of the EEPROM is to pin capacitance (10 picofarads)- is this one and the same?

Yes. Plus the MCU capacitance and also the PCB stray capacitance and PCB trace capacitance.. I would keep a margin of extra 20pF for those other than device parasitics.

Question 4 Minimum and maximum pull-up values Assume pull up is strong (low value resistance). When the MCU outputs a low, there is connection between VCC--->pull up resistor value--->MCU pin--->nMOSFET of the pin of MCU (which is on) ---> ground.

In this case MCU sinks more current. This also means that MCU starts building voltage at the output pin (outputting low). This voltage is due to ohmic loss across the nMOSFET of the MCU pin.. It will have a finite resistance. Hence, the output voltage of MCU will not be true zero but a few 100 mV (an example) which should be still within its VOL specification.

To case of weak pull up (very high resistor value, say 100kohms) Assume the EEPROM clock input current is 10uA. It can be higher also.

When the MCU drives the clock pin high, MCU actually releases the clock pin.. EEPROM sees high because of VCC.. But what exactly will be the voltage at the clock input of the EEPROM?

Let's see If VCC is 3.3 V.. Then due to clock pin input current of 100uA there will be drop of 10 uA * 100k across the resistor, which is 1000mV or 1V.. So voltage across clock pin will be only 2.3V.. Hence, one has to care for input high voltage when choosing weak pull up resistor.

More importantly, if the resistance is too high, chances of failing the protocol required rise time will be more.

\$\endgroup\$
  • \$\begingroup\$ "Rise time will be five times RC. Here, it will be 5us." That's a bit pessimistic - that is the time to reach 99% of final voltage. Rise time is normally considered to be 10% to 90% which is usually approximated by 2.2 * RC. \$\endgroup\$ – Kevin White Jun 16 '18 at 20:48
  • \$\begingroup\$ @KevinWhite Rise time for I2C is considered from 30% to 70%.. I was only trying to relate things. \$\endgroup\$ – Umar Jun 17 '18 at 4:33
1
\$\begingroup\$

Unless you are doing something unusual (like running at extreme frequency or have an extremely long, and hence capacitive, bus) - it should not be a deal. Values between around 1k and 10k are usual. Check the device datasheets for recs, try what they recommend, have a quick look with the scope that things look OK, and if it works - don't mess with it.

\$\endgroup\$
1
\$\begingroup\$
  1. "The \$V_\mathrm{OL}\$ level that can be read as a valid logical low by the input buffers" so it corresponds to the worst case output from the device. You have to pick \$V_\mathrm{OL}\mathrm{(max)} < V_\mathrm{IL}\mathrm{(max)}\$ for the circuit to function robustly.

  2. Bus capacitance is the total capacitance on the whole I2C line. It is the sum of the pin capacitances, and any parasitic capacitances. Your reading of the datasheet is correct, and 10 pF is a reasonable value. All the pins on a bus sum in parallel, so the more ICs you have, the greater the capacitance.

  3. This is because the output will actually be at \$V_\mathrm{OL}\$ not 0 V, so it makes sense to go from there.

  4. I didn't see the reference to weak pull ups? Ultimately, it doesn't matter if you consider it from output or input, as long as you reach the required conclusion.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.