In I2C protocol, the device operate in open collector or open drain mode. The devices (both microcontroller and the EEPROM) can drive the pins to logic zero (strong zero, assume as if they literally take the lines and short it to ground).
The logic one is merely achieved by the pull ups which are provided externally. Pull up resistor is in kilo ohms. (We will seethe values in a moment). There will be parasitic capacitance on the bus due to multiple I2C devices connected, PCB stray capacitance etc..
When signal is going high, the current has to flow from VCC through the pull up resistor and to the IC pins. So, the RC time constant kicks in.. It makes the rise of the signal sloppy. Example, if capacitance is 100pF and pull up is 10kohms.. Rise time will be five times R*C. Here, it will be 5us.
The fall time will not b an issue because, it will be almost instant.. From the IC pins to ground.. There is no resistors in the path to delay.
It talks of bus capacitance: the only reference I can find on the
datasheet of the EEPROM is to pin capacitance (10 picofarads)- is this
one and the same?
Yes. Plus the MCU capacitance and also the PCB stray capacitance and PCB trace capacitance.. I would keep a margin of extra 20pF for those other than device parasitics.
Minimum and maximum pull-up values
Assume pull up is strong (low value resistance).
When the MCU outputs a low, there is connection between VCC--->pull up resistor value--->MCU pin--->nMOSFET of the pin of MCU (which is on) ---> ground.
In this case MCU sinks more current. This also means that MCU starts building voltage at the output pin (outputting low). This voltage is due to ohmic loss across the nMOSFET of the MCU pin.. It will have a finite resistance. Hence, the output voltage of MCU will not be true zero but a few 100 mV (an example) which should be still within its VOL specification.
To case of weak pull up (very high resistor value, say 100kohms)
Assume the EEPROM clock input current is 10uA. It can be higher also.
When the MCU drives the clock pin high, MCU actually releases the clock pin.. EEPROM sees high because of VCC.. But what exactly will be the voltage at the clock input of the EEPROM?
Let's see If VCC is 3.3 V.. Then due to clock pin input current of 100uA there will be drop of 10 uA * 100k across the resistor, which is 1000mV or 1V.. So voltage across clock pin will be only 2.3V.. Hence, one has to care for input high voltage when choosing weak pull up resistor.
More importantly, if the resistance is too high, chances of failing the protocol required rise time will be more.