I am trying to connect one of my VHDL blocks to a Xilinx generated block (a dual port RAM).
The problem is that the write enable of the RAM is defined as an std_logic_vector(0 down to 0) instead as a std_logic and I do not know how to connect them.
The RAM block:
component bloque_4 port( ... wea : in std_logic_vector(0 downto 0); ... ); end component;
Whereas the component that tries to write into that memory is:
component bloque_3 port( ... write_en_b3 : out std_logic; ... ); end component;
In the test bench I wrote for testing the connection I defined a signal for establishing the communication between the two of them:
signal write_en_b34 : std_logic;
So far things are great, the problem comes when I try to map the write_en_b34 signal to the wea port.
uut: bloque_4 port map ( ... wea => write_en_b34, .. );
I understand there is a type mismatch, but I do not know how to solve it. So, how could map a std_logic_vector(0 downto 0) to a std_logic??