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Hi I'm trying to design a multiprocessor in Verilog.

`timescale 1ns / 1ps

module Microprocessor(
    input [7:0] instruction,
    input clock,
    input reset,
    output [7:0] nextAddr,
    output [6:0] seg1,
    output [6:0] seg2
    );

     //wire [1:0] instructionTemp;
     wire [7:0] nextAddrTemp;
     reg     [1:0] writeReg;
     wire regDst;
     //wire regData;
     wire aluSrc;
     //wire aluResult1;
     wire memR;
     wire memW;
     wire [7:0] readData1;
     wire [7:0] readData2;
     reg [7:0] readData3;
     wire [7:0] aluResult;
     wire [7:0] readData;
     reg [7:0] writeData;
     wire regW;
     wire [7:0] regData;
     wire aluOp;
     wire branch;
     wire [1:0] instruction76;
     wire [1:0] instruction54;
     wire [1:0] instruction32;
     wire [1:0] instruction10;
     reg [1:0] dest;
     wire m2r;

     wire [7:0] instruction70;

     assign instruction76 = instruction[7:6];
     assign instruction54 = instruction[5:4];
     assign instruction32 = instruction[3:2];
     assign instruction70 = instruction[7:0];
     assign instruction10 = instruction[1:0];

pc uut1(.clock(clock),.reset(reset),.isBranch(branch),.dest(dest),.count(nextAddr));
controlUnit uut2(.clock(clock),.inst(instruction76),.branch(branch),.m2r(m2r),.memR(memR),.memW(memW),.aluOp(aluOp),.regW(regW),.aluSrc(aluSrc),.regDst(regDst));
dataMemory uut3(.clock(clock),.reset(reset),.memR(memR),.memW(memW),.writeData(readData2),.address(aluResult),.readData(readData));
bcdDisplay uut4(.bcd(regData[7:4]),.seg(seg1));
bcdDisplay uut5(.bcd(regData[3:0]),.seg(seg2));
register uut6(.readReg1(instruction54),.readReg2(instruction32), .writeReg(writeReg), .writeData(writeData), .regWrite(regW),.clock(clock), .readData1(instruction54),.readData2(instruction32),.regData(regData));
ALU uut7(.ALUOp(aluOp),.clock(clock),.readData1(readData1),.readData2(readData3),.result(aluResult));   
IMEM uut8(.Instruction(instruction70),.Read_Address(nextAddr));

    always@(posedge clock)begin
        case(instruction10)
            2'b10:
              dest <= -2;
            2'b11:
              dest <= -1;
            default:
              dest <= instruction10;
            endcase
        end

    always@(posedge clock)begin     
        case(regDst)
            1'b1:
                writeReg <= instruction10;
            1'b0:
                writeReg <= instruction32;
        endcase
    end

    always@(posedge clock)begin
        case(aluSrc)
            1'b1:
                readData3 <= dest;
            1'b0:
                readData3 <= readData2;
        endcase
    end

    always@(posedge clock)begin
        case(m2r)
            1'b1:
                writeData <= readData;
            1'b0:
                writeData <= aluResult;
        endcase
    end


endmodule

When I run this code with the sub-module codes included, I get the following error

ERROR:Xst:528 - Multi-source in Unit <Microprocessor> on signal <instruction<5>>; this signal is connected to multiple drivers.
Drivers are: 
   Primary input port <instruction<5>>
   Signal <uut6/readData1<1>> in Unit <register> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Microprocessor> on signal <instruction<4>>; this signal is connected to multiple drivers.
Drivers are: 
   Primary input port <instruction<4>>
   Output port doB<0> of instance <uut6/Mram_register> of inferred macro RAM

ERROR:Xst:528 - Multi-source in Unit <Microprocessor> on signal <instruction<3>>; this signal is connected to multiple drivers.
Drivers are: 
   Primary input port <instruction<3>>
   Signal <uut6/readData1<1>> in Unit <register> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <Microprocessor> on signal <instruction<2>>; this signal is connected to multiple drivers.
Drivers are: 
   Primary input port <instruction<2>>
   Output port doB<0> of instance <uut6/Mram_register_ren> of inferred macro RAM

I noticed most of my errors occur in the Register module, so I will also upload the register module.

`timescale 1ns / 1ps

module register(
    input [1:0] readReg1,
    input [1:0] readReg2,
    input [1:0] writeReg,
    input [7:0] writeData,
    input regWrite,
    input clock,
    output [7:0] readData1,
    output [7:0] readData2,
    output reg[7:0] regData //goes to BCD!
    );
    reg [3:0] register[7:0];
    wire readData1wire;
    wire readData2wire;


    assign readData1wire = register[readReg1];
    assign readData2wire = register[readReg2];

    always@(posedge clock)begin
    if(regWrite==1)begin
        register[writeReg] <= writeData;
    end
    regData <= writeData;
    end

    assign readData1 = readData1wire;
    assign readData2 = readData2wire;

endmodule

I noticed that that kind of error occurs when you're trying to assign values to the same variable multiple times in several always() loops. However I don't think I didn't do that in my code. Any kind of help would be appreciated. Thanks!

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  • \$\begingroup\$ Cross posting is very much frowned up. I just left a comment on the SE site and find the same question here. I am not amused! \$\endgroup\$ – Oldfart Jun 17 '18 at 10:36
  • \$\begingroup\$ Sorry I didn't know it was banned to post simultaneously :( I will delete the one on SE I am very sorry. \$\endgroup\$ – Peter Jun 17 '18 at 12:05
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Your problem is that you have multiple drivers of a signal. Specifically caused by this line (I've taken the liberty of formatting it in a sensible way):

register uut6(
    .readReg1(instruction54),
    .readReg2(instruction32),
    .writeReg(writeReg),
    .writeData(writeData),
    .regWrite(regW),
    .clock(clock),
    .readData1(instruction54),
    .readData2(instruction32),
    .regData(regData)
);

Your readData1 and readData2 signals are outputs from the register module. You connect these to instruction54 and instruction32 respectively. However these two signals are already driven by assign statements:

 assign instruction54 = instruction[5:4];
 assign instruction32 = instruction[3:2];

As such you have two sources driving the same signal.


Additionally, while not your specific issue, there is a mistake in the register module. Your signals readData1wire and readData2wire are declared as 1-bit wide, but you use them to connect two 8-bit signals. To be honest, I'm not sure why those signals are used at all, just assign to readData1 and readData2 directly.

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