# 7 segment display for hexadecimal numbers using PLAs

I'm trying to design 7 segment display for single digit hexadecimal numbers using PLAs but I am getting more than 16 product terms .If I implement using PROM it uses exactly 16 product terms(all min-terms). My question is:

1.Is there a calculation error from my end when I'm getting more than 16 prod terms. 2.IF 1 is not true, then is it that in this case using PROM is better option than using a PLA.As it requires lesser hardware.

I'm not actually using an IC but trying out the designs on paper.Please let me know if any clarifications are required.

• It would be helpful to include the product terms you found in the question, so please use the edit button to do that now. Have you minimized your equations? Are you treating each segment as an independent problem, or do you believe you've found some overlap of pattern that is worth leveraging? Jun 19, 2018 at 4:47
• @ChrisStratton I have minimized using K MAP,No not treating them as individual problem , that I will be doing in next part for PALs, Here I am trying to find as many overlaps as possible (circled), still it is exceeding 16 terms. Jun 19, 2018 at 5:13
• You can do it in 14 product terms, I think. Are you expecting to use active LOW or active HIGH for the segments?
– jonk
Jun 19, 2018 at 6:54
• You aren't minimizing for total product terms. You are just minimizing each segment, separately.
– jonk
Jun 19, 2018 at 7:18

My minimization is:

\begin{smallmatrix} \begin{array}{l|l} \begin{array}{l} \begin{array}{l} Z_0 \:=\: \overline{B_3}\: B_1\: B_0\\ Z_1\: =\: B_3\: B_2\: B_1\\ Z_2 \:=\: \overline{B_3}\: B_2\: \overline{B_1} \:B_0\\ Z_3\: =\: \overline{B_3}\: \overline{B_2}\: \overline{B_0}\\ Z_4 \:=\: B_3\: \overline{B_2}\: \overline{B_1}\\ Z_5\: =\: \overline{B_3}\: B_2\: B_1\: \overline{B_0}\\ Z_6\: =\: B_3\: B_2 \:\overline{B_0}\\ Z_7\: =\: B_3\: \overline{B_2}\: \overline{B_0}\\ Z_8\: =\: \overline{B_3}\: \overline{B_1}\: \overline{B_0}\\ Z_9\: =\: \overline{B_3}\: B_2\: \overline{B_0}\\ Z_{10} =\: \overline{B_3}\: \overline{B_2}\: B_1\\ Z_{11} =\: B_3 \:B_2\: \overline{B_1}\: B_0\\ Z_{12} =\: B_3\: \overline{B_2} \:B_1\: B_0\\ Z_{13} =\: \overline{B_2}\: \overline{B_1} \end{array} \end{array} & \begin{array}{l} \begin{align*} A\: &=\: Z_0 + Z_1 + Z_2 + Z_3 + Z_4 + Z_5 + Z_6 + Z_7\\ B\: &=\: Z_0 + Z_3 + Z_7 + Z_8 + Z_{11} + Z_{13}\\ C\: &=\: Z_0 + Z_2 + Z_5 + Z_7 + Z_8 + Z_{11} + Z_{12} + Z_{13}\\ D\: &= \: Z_2 + Z_3 + Z_4 + Z_5 + Z_6 + Z_{10} + Z_{11} + Z_{12}\\ E\: &= \: Z_1 + Z_3 + Z_5 + Z_6 + Z_7 + Z_{11} + Z_{12}\\ F\: &= \: Z_1 + Z_2 + Z_4 + Z_5 + Z_6 + Z_7 + Z_8 + Z_{12} \\ G\: &= \: Z_1 + Z_2 + Z_4 + Z_9 + Z_{10} + Z_{11} + Z_{12} \end{align*} \end{array} \end{array} \end{smallmatrix}

## A SUGGESTION

I was a little disappointed in the work you put into the question. Partly, because I wasn't sure what you wanted. It has arrived now through a series of comments. But it would be nice if you'd anticipated it, earlier. Partly, because you only provided an image of your handwriting, but no particular clarity about your full table or the active sense of the A-G outputs. Sure, that can be inferred. But, why should we have to?

So in the interest of making the above point, let me add here what I think you might have considered adding to your question before asking it.

Here is a possible table and set of K-maps. I've included a "don't care" where I'm not sure about what you need there.

$$\begin{smallmatrix} \begin{array}{cccc|ccccccc} B_3&B_2&B_1&B_0&A&B&C&D&E&F&G\\ \hline 0&0&0&0&1&1&1&1&1&1& \\ 0&0&0&1& &1&1& & & & \\ 0&0&1&0&1&1& &1&1& &1\\ 0&0&1&1&1&1&1&1& & &1\\ 0&1&0&0& &1&1& & &1&1\\ 0&1&0&1&1& &1&1& &1&1\\ 0&1&1&0&1& &1&1&1&1&1\\ 0&1&1&1&1&1&1& & &X&\\ 1&0&0&0&1&1&1&1&1&1&1\\ 1&0&0&1&1&1&1&X& &1&1\\ 1&0&1&0&1&1&1& &1&1&\\ 1&0&1&1& & &1&1&1&1&1\\ 1&1&0&0&1& & &1&1&1&\\ 1&1&0&1& &1&1&1&1& &1\\ 1&1&1&0&1& & &1&1&1&1\\ 1&1&1&1&1& & & &1&1&1 \end{array} \end{smallmatrix}$$

K-maps:

$$\begin{array}{rl} \begin{smallmatrix}\begin{array}{r|cccc} A&\overline{B_1}\:\overline{B_0}&\overline{B_1}\: B_0&B_1 \:B_0&B_1 \:\overline{B_0}\\ \hline \overline{B_3}\:\overline{B_2}&1&0&1&1\\ \overline{B_3}\:B_2&0&1&1&1\\ B_3\: B_2&1&0&1&1\\ B_3\:\overline{B_2}&1&1&0&1 \end{array}\end{smallmatrix} & \begin{smallmatrix}\begin{array}{r|cccc} B&\overline{B_1}\:\overline{B_0}&\overline{B_1}\: B_0&B_1\: B_0&B_1 \:\overline{B_0}\\ \hline \overline{B_3}\:\overline{B_2}&1&1&1&1\\ \overline{B_3}\:B_2&1&0&1&0\\ B_3\: B_2&0&1&0&0\\ B_3\:\overline{B_2}&1&1&0&1 \end{array}\end{smallmatrix}\\\\ \begin{smallmatrix}\begin{array}{r|cccc} C&\overline{B_1}\:\overline{B_0}&\overline{B_1}\: B_0&B_1\: B_0&B_1 \:\overline{B_0}\\ \hline \overline{B_3\:}\overline{B_2}&1&1&1&0\\ \overline{B_3}\:B_2&1&1&1&1\\ B_3\: B_2&0&1&0&0\\ B_3\:\overline{B_2}&1&1&1&1 \end{array}\end{smallmatrix} & \begin{smallmatrix}\begin{array}{r|cccc} D&\overline{B_1}\:\overline{B_0}&\overline{B_1}\: B_0&B_1\: B_0&B_1\: \overline{B_0}\\ \hline \overline{B_3}\:\overline{B_2}&1&0&1&1\\ \overline{B_3}\:B_2&0&1&0&1\\ B_3\: B_2&1&1&0&1\\ B_3\:\overline{B_2}&1&X&1&0 \end{array}\end{smallmatrix}\\\\ \begin{smallmatrix}\begin{array}{r|cccc} E&\overline{B_1}\:\overline{B_0}&\overline{B_1}\: B_0&B_1\: B_0&B_1\: \overline{B_0}\\ \hline \overline{B_3}\:\overline{B_2}&1&0&0&1\\ \overline{B_3}\:B_2&0&0&0&1\\ B_3\: B_2&1&1&1&1\\ B_3\:\overline{B_2}&1&0&1&1 \end{array}\end{smallmatrix} & \begin{smallmatrix}\begin{array}{r|cccc} F&\overline{B_1}\:\overline{B_0}&\overline{B_1}\: B_0&B_1\: B_0&B_1\: \overline{B_0}\\ \hline \overline{B_3}\:\overline{B_2}&1&0&0&0\\ \overline{B_3}\:B_2&1&1&X&1\\ B_3\: B_2&1&0&1&1\\ B_3\:\overline{B_2}&1&1&1&1 \end{array}\end{smallmatrix}\\\\ \begin{smallmatrix}\begin{array}{r|cccc} G&\overline{B_1}\:\overline{B_0}&\overline{B_1}\: B_0&B_1\: B_0&B_1\: \overline{B_0}\\ \hline \overline{B_3}\:\overline{B_2}&0&0&1&1\\ \overline{B_3}\:B_2&1&1&0&1\\ B_3\: B_2&0&1&1&1\\ B_3\:\overline{B_2}&1&1&1&1 \end{array}\end{smallmatrix} \end{array}$$

Had you provided these, or something similar, your question would have been greatly improved. And it would have saved me time I should not have had to spend on your behalf.

I know you meant well. And I'm not meaning to be overly-critical. I'm just suggesting that saving the time of others is basic consideration, good etiquette, and perhaps even a moral duty. One should put all necessary time into the question, even adding things felt to be almost unnecessary details. Because if it saves just a few minutes of time for others it is very much worth doing.

As it is, I've had to add this in order to set the context needed to make my own answer clearer.

## APPROACH

For now, I'm holding short. Because of the price I already paid in laying out the above, I'll have to come back to this when I'm back in the mood and have the available time to dive in, again. For now, perhaps you can look over the tables and see if I made any mistakes. Also, see if the answer at the top appears to achieve the goal.

In the meantime, perhaps you can also consider reading An Algorithm for Multiple Output Minimization, by Gurunath and Biswas, 1989.

• +1 Astounding answer, even by your standards. Jun 20, 2018 at 22:29
• @jonk Many Many Thanks. I will keep your suggestions in mind. Its people like you that make this community such great, and next time,by any chance yyo find a question by me, It will be clear and to the point. Thanks again. cheers! Jun 21, 2018 at 18:55

You do not deed to solve K MAPs, that usually results in more, although simpler, terms when dealing with multiple outputs. You only need a sum of products in canonical form.

Look at the description of the Programmable Logic Array on wikipedia. With 4 inputs you have 2^4 == 16 AND gates allowing you to cover all the possible 4 bit inputs. That turns the AND part into a simple 4 bit address decoder. And then you simply implement your truth table in the OR part.

You can optimize terms. Jonk mentioned you can do it in 14 terms. But with the PLA having 16 terms not using 2 of them gains you nothing but more work optimizing the terms. So why bother? Makes me wonder why the AND part is even programmable.

• I pretty much agree with you on this. I was (and still am) a little mystified about why there is even a question by the OP here. It's obvious how to get to 16 terms!! So what's the real question and why?
– jonk
Jun 19, 2018 at 15:51
• @jonk Its like most of the time PLA are considered better, but In this case it turns out that PROM is better to use,But I need some suggestions from someone more experienced than me, Thanks to you and Goswin. Jun 19, 2018 at 18:53
• @Siddharth So, are you really asking for a way to find the 14 terms? Is that the real question? A process to follow to minimize the total number of product terms? (Because you followed ONLY a method to minimize each term separately. Which is NOT how you'd approach the question of minimizing the total product term count.)
– jonk
Jun 19, 2018 at 19:27
• And don't forget that if you have e.g. 2 PLAs with 4 outputs each then you can optimize 4 outputs as a group and 3 outputs as another group separately. But say after hours of testing how to split up the outputs of the 2 PLAs you find a solution with 14 or less terms what then? You still need 2 PLAs and any unused terms in the PLAs can't be used any other way. Jun 19, 2018 at 21:05
• @jonk Actually no, I was not looking for a number but now I am curious how to get the terms. I'm following the method where I reduce the product terms for each segment separately and then look for the common terms but i got stuck as it exceeded 16 terms. Jun 20, 2018 at 2:55