# register enable line usage in case block (verilog synthesis for altera cpld)

I have the following in a verilog design aimed at an altera CPLD (currently targeting EPM240, although the target device isn't set in stone):

always @(posedge clk)
if (we)
begin
case (rw_sel)
3'd0: reg0 <= data_in;
3'd1: reg1 <= data_in;
...
endcase
end

I assumed that this would synthesize a design where rw_sel was decoded into a number of different select lines, which would be 'and'ed with we, and then connected to the enable input of the register.

However, this isn't what has been done: examining the results in the RTL viewer, the we line has been connected directly to the enable inputs of every register, then the data input of each register is connected to a mux2 that selects from either the incoming data or the current value of the register.

Isn't this much less space-efficient than the design I was expecting? And if so, how can I persuade Quartus to generate the more efficient version?