Given a common setup:
The green box is a PCB mainly consisting of a data acquisition device (ADC+RF frontend) which is controlled by a Spartan-6 FPGA.
The ADC & FPGA use a clock from a Tektronix signal generator which itself is configured to take the 10 MHz reference clock from a R&S SMW200A Vector Signal Generator.
Data acquisition is started from a laptop which sends a trigger event to the FPGA. Internally, the FPGA has multiple clocks but all of them are synchronuous to (and generated from) the 80 MHz clock.
The trigger event is synchronized to the respective FPGA clocks and start ADC capture. Furthermore, the "Trigger Signal" is synchronized to the FPGA slowest clock and stretched.
The SMW200A is configured to start outputting data exactly at this "Trigger Signal". Assuming all clocks are synchronized, all delays should be fixed for each trigger event.
However, this is the captured data for multiple runs:
The data always starts at either 118.5us or 118.75us delay. The difference is exactly one ADC sample (ADC is 4 MSps but uses the 80 MHz clock).
Now I am trying to figure out what could be wrong here.
- Does the output of the SMW200A always start exactly after a constant time after the trigger is applied (I don't think so).
- Is the trigger on the SMW synchronized to an internal clock? If so, which clock is this?
- How can this clock be synchronized with the rest of the system? (I assume the 10 MHz reference clock sharing only makes sure that that all systems share the same frequency uncertainties)