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I have a simple logic circuit requirement, but can't seem to match any standard flip-flop or latch to my needs (SR, JK, D, MS, level-sensitive or clocked, etc).

The circuit is to disable a H-bridge driver IC if an over-current situation is detected (via a Allegro ACS770 analog-output hall-effect current sensor input to a window comparator, creating the OverCurrent logic-level).

The DISable signal must stay active even if OverCurrent falls back to inactive, until the BridgeEnable is at least deactivated, or optionally deactivated and then reactivated.

Inputs:

BE (BridgeEnable), active-high.

OC (OverCurrent), active-high or active-low, I can flip the comparators either way.

Output:

DIS (Disable), ideally active-low.

This timing-diagram shows the functionality I'm looking for: Timing-Diagram needed

Suggestions?

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You can use a standard SR latch. When you make them out of 2 NOR gates, the 1,1 input state, often thought of as pathological to people just wanting a latch, actually performs the logic operation you are looking for.

schematic

simulate this circuit – Schematic created using CircuitLab

I'll let you draw out the truth table properly and confirm that it does what you want.

Note that NOR1 always outputs 0 if overcurrent is true, regardless of what BE is doing. And DIS is active low!

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  • \$\begingroup\$ duh! thanks for that, can't believe I didn't invert the BE and see the truth-table resemblance to what I needed. and yeah, the 'pathological' avoidance of two 1s (or 2 0s in a NAND S-R) isn't necessarily a deal-breaker, thank for clearing that up for me! \$\endgroup\$ – Techydude Jun 21 '18 at 19:24
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You can use a D-register with an active low reset. (Or active high reset and add an inverter).
- Connect the data input high (1)
- Connect the BE to the (active low) reset.
- Connect the OC to the clock.

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