I would like to incorporate this circuit in my design so that I could use a low current capacity slide switch to control the 2A current of a Li-poly.

Now, I understand the purpose of having two PMOS for bidirectional current control as discussed here and the purpose of the zener diode D2 for clamping the gate voltage to a voltage below the maximum allowable voltage of the gate as discussed here.

Finally, the BJT Q3 allows for controlling the gates of the two PMOS through a GPIO pin.

But what is the purpose of R3 in this circuit? (Can it be ommited?)

reverse voltage protection circuit

EDIT: Of course, how did I not see that from the start? To be honest it seemed strange to me that R3 was pulled up to the path between Q1 and Q2 rather that to Vin , but now I understand that it is only between Q1,Q2 that one can be sure there is a path to the supply, since the circuit works biderectionally (i.e if voltage was applied from Vout and R3 was pulled up to Vin, the top end of R3 would be floating).

Thanks for the replies


R3 is the essential pullup to Q3 to turn off the MOSFET pair with R2 in series .

The purpose of this circuit is to replace a diode voltage drop for Reverse Battery Protection with 2 series high current low RdsOn switches to minimize drop voltage during battery charging.

In the fine print it offers two different Zener voltages ; LV and SV because standard threshold FETs (2~4V) have an absolute max of |Vgs|=20 so the higher Vz is needed, and sub-threshold FETs Vr<2V need Vgs=2.5Vt and lower Vgs Abs Max.

Not all FETs have the same threshold to switch on. For a low voltage pack, a low Vgs(th) or logic level type FETs would be used and for high series cell packs a std threshold FET may be used. But they need 2.5 times their threshold to conduct near rated RdsOn and 3x threshold for std FETs (2~4V threshold)

  • \$\begingroup\$ Tony is that a similar function to the flyback diode used in parallel to motors to protect against EMF? \$\endgroup\$ – Geo Jun 21 '18 at 11:21
  • \$\begingroup\$ Not quite , in that case the diode is also parallel to the coil to conduct stored current when switched off and polarity reverses. This zener actually serves to limit Vgs when the battery pack is > 15V when cct is switched ON . My answer was speculative, but I now see the fine print for SV (std. Vgs=+-20max) so large battery strings are possible and choice of FET have SV or LV breakdown thresholds. \$\endgroup\$ – Tony Stewart EE75 Jun 21 '18 at 12:03
  • \$\begingroup\$ Thanks for editing your answer, I can now understand why they use the different values for LV and SV. However I find it hard to understand how the two series PMOS can ever be off, if the zener is constantly clamping Vgs at, let's say, -6.2V. If the zener was not there, by placing the battery backwards I would force the mosfet gates HIGH and the channels would be off. But with the zener the channels will always be on even if the battery is placed backwards. What am I getting worng here? \$\endgroup\$ – Geo Jun 21 '18 at 12:48
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    \$\begingroup\$ There is no connection between the drains on either side to the common Gates except internal Miller Capacitance. Therefore if Q3 is off there is no load Condition that can force both FETs ON If load goes negative by reversed Bat. Although high dV/dt connecting one side backwards may cause that side to conduct momentarily, but not permanently with DC bias on -Vgs. to enable both FETs. So again R3 and R2 are essential for operating “off” and Zener is just OVP to gate max Vgs \$\endgroup\$ – Tony Stewart EE75 Jun 21 '18 at 14:03
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    \$\begingroup\$ At least someone understands without a grudge TY \$\endgroup\$ – Tony Stewart EE75 Jun 21 '18 at 14:51

Laptop2d nailed it, but I'll restate it in a different way in case that helps.

Remember that a Mosfet gate is like a capacitor. If you don't pull it one way or another it will just float wherever.

You'll notice that the BJT, and the 2 switches can only pull the mosfet gate down. Without R3 there is nothing to pull the gate back up again and it will just stay down, or float about uncontrolled.

Think about what would happen if instead the switches and transistor were in a push-pull configuration, where they could pull the gate both ways. If one switch was ON and another was OFF, they would fight each other and short out. This configuration avoids that.

  • \$\begingroup\$ Actually we all ignored that R2 is essential for pullup too and without it R3 cannot touch the gates \$\endgroup\$ – Tony Stewart EE75 Jun 21 '18 at 11:39
  • \$\begingroup\$ Ie your analogy of the nail or analysis hitting the target therefore is bent . R3 carries “no power “ , certainly no more than R2 +R3 and Q3 or about a microwatt , so I would edit out that he nailed it. Because he did not. It’s important to correct your own mistakes as I just did \$\endgroup\$ – Tony Stewart EE75 Jun 21 '18 at 12:27
  • \$\begingroup\$ I would consider R3 to be the "pull-up" and R2 to be a current limiting resistor. Why R2 is so large, I don't know. I would have put a 10k in there max. \$\endgroup\$ – Drew Jun 21 '18 at 15:06
  • \$\begingroup\$ The Ciss of both FETs and R3+R2 form a slow turn off time to prevent false triggering from some FETs with high Miller capacitance self trigger due to dV/dt rise. \$\endgroup\$ – Tony Stewart EE75 Jun 21 '18 at 15:10

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