Why is the input voltage of transistors in the CMOS circuit set to Vdd when calculating the equivalent resistance?

Question

When deriving the equivalent resistance formula of NMOS inverter the graph which is used in derivation is as shown:

$$R_{eq} = \frac{1}{-V_{dd}/2} \int_{V_{dd}}^{V_{dd}/2} \frac{V}{I_{Dsat}(1+\lambda V_{dd})} dx \approx \frac{3}{4}{V_{dd}}{I_{dsat}}(1-\frac{7}{9}\lambda V_{dd})$$ When calculating the equivalent resistances of NMOS and PMOS transistors in a CMOS inverter i was instructed to use this formula and for the saturated current which plays a part to take $$I_{Dsat}=\frac{B}{2}(V_{gs}-V_t)^2 = \frac{B}{2}(V_{dd}-V_t)^2$$ where B is a property of the transistor.

Why is Vdd taken as the gate-source voltage of both transistors for the saturated current if neither is in saturation at that point on the V(output)=V(V(input)) graph of CMOS inverter and why is it used in the derivation in the first place? How is it connected to the resistance which we want?

Edit: The resistance i'm asking for is the dynamic resistance of the transistor used when calculating the time-delay of the rising and falling edge of the graph. The equations of time-delay are given as: $$tp_{HL}=0.69R_{eqn}C_l$$ where Cl is the capacitance of the inverter and tpHL is the time for output voltage to go from logical 1 to logical 0 (highest and lowest voltage). This "discharging" of the transistor is done by the NMOS transistor so Reqn is it's dynamic resistance. Similar is with Reqp (tpLH). The formulas above are connected to this Reqn and Reqp but i don't understand the way it's calculated and why it uses Vdd for both transistors when calculating the saturated current when they are not in a state of saturation at that voltage, rather NMOS is linear and PMOS is turned off.

Answer 1

We assume that the input to a CMOS gate is driven by another CMOS gate, and that the output of a CMOS gate is either at \$V_{DD}\$ for a logic 1 or at ground for a logic 0. We also (usually) assume that the sources of all NMOS transistors are tied to ground and that the sources of all PMOS transistors are tied to \$V_{DD}\$.

Another simplifying assumption is that the inputs of the logic gate that you wish to analyze are stable and at either \$V_{DD}\$ or ground. If the input is at \$V_{DD}\$ then the PMOS transistors are cut off and we are only interested in what the NMOS transistors are doing. Since the NMOS source is at ground we use $$V_{GSN} = V_G - V_S = V_{DD} - 0 = V_{DD}$$ If you assume that the logic gate input is at ground then the NMOS is cut off and \$V_{GSP} = -V_{DD}\$.

Of course, that's a lot of simplifying assumptions. The dynamic behaviour is much more complex, and the effective \$R_{DS}\$ changes as the logic gate's output voltage (and hence the transistor's \$V_{DS}\$) changes. If you really want good answers, simulate in SPICE with accurate input rise/fall times and parasitic capacitances. For back-of-the envelope calculations you could approximate \$R_{DS}\$ with something like twice the effective \$R_{DS}\$ when \$V_{DS} = V_{DD}\$ but this would be really crude. The \$R_{MID}\$ in your first graph is another approximation using \$I_{DS}\$ when \$V_{DS} = V_{DD}/2\$.

The bottom graph that you provide illustrates dc behavior and isn't very relevant for transient switching behavior.