I've long wondered how an RS-latch can work, given the existence of propagation delays.

nor-based RS-latch

If the nor-gates have non-zero propagation delays (aka gate delays), wouldn't it need to be the case that:

  1. The inputs to each are held stable during the propagation delay?
  2. The outputs should not be used as inputs until after the propagation delay has passed with unchanging inputs?

This differs from other questions about RS-latches, which do not consider propagation delay:

Consider the below picture, which illustrates the transition from {R=0, S=1} to {R=1, S=0}. After the transition is made, won't Q and Q' temporarily enter the forbidden region? When those bad values enter the other gates, won't those (possibly) enter the forbidden region, causing garbage to propagate?

Sequence of RS-latch states.


2 Answers 2


Yes, you are correct. The inputs must be held in a stable state until any change propagates through both gates, and the outputs may be inconsistent during that time.

We usually design circuits with edge-triggered flip-flops, and the corresponding notions are the setup time, hold time, and clock-to-Q delay. The setup and hold time specifications indicate a window of time around the edge of the clock signal where the input must remain stable. The clock-to-Q time is the delay from a clock edge until the output is valid.

When doing a full synchronous system design these requirements combine, along with the logic delay, to determine the minimum clock period. If you absolutely must have output signals that are always valid then you need to use an output register that loads them once they are guaranteed to have settled to their valid values.

  • 1
    \$\begingroup\$ Thank you, but I was taught (and have taught) that edge-triggered flip-flops are built out of latches, so it seems that flip-flops would be nondeterministic if latches are. (I know I must be missing something.) \$\endgroup\$ Commented Jun 21, 2018 at 18:45
  • \$\begingroup\$ Flip-flops are built from latches, and if you violate the setup and/or hold time then the behavior is nondeterministic. This is called "metastability" and it can be big problem if you have asynchronous inputs to a synchronous system. Your intuition is spot on. \$\endgroup\$ Commented Jun 21, 2018 at 19:32
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    \$\begingroup\$ @EllenSpertus: If one builds flip flop with two latches as its primary components, one will need a gate whose output-disturb time is guaranteed to be at least as long as the worst-case propagation time of some combinations of gates within the latches. It is not possible to build a flip flop entirely out of gates which do not specify a minimum delay between a disturbance on an input and a disturbance on the output \$\endgroup\$
    – supercat
    Commented Jun 21, 2018 at 22:15
  • \$\begingroup\$ @supercat Thank you. This is the first I've heard of "output-disturb time". I don't recall ever seeing that on a datasheet (e.g., futurlec.com/74LS/74LS02.shtml, which just has Tphl and Tplh). \$\endgroup\$ Commented Jun 21, 2018 at 22:25
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    \$\begingroup\$ @supercat I have to agree with Ellen Spertus. I've been doing this for decades and never heard of "output disturb time". Sounds like the "contamination delay" from Harris texts. Data sheets commonly specify only maximum propagation delay for a gate. Flip-flops may provide a minimum time that data remains stable after the clock, but for logic gates we assume that the gate output starts changing as soon as the input changes. \$\endgroup\$ Commented Jun 22, 2018 at 10:46

All real-world devices have non-zero propagation delays. In fact an RS latch would not work without a few nano-seconds delay.

Assuming both inputs are '0' and the latch contains the last state entered, you will find the datasheets (74HC02/74LS02) specify a minimum positive pulse (logic '1') to any input for it to change state. This minimum time is needed to overcome that propagation delay and force the latch to change state.

Likewise, the same datasheets will tell you that holding both inputs at logic '1', which holds both outputs at logic '0', and then making them low at the same time results in an unknown output state.

You can only toggle output states if one input is held low while another is set to logic '1' for the minimum setup time.

To elaborate on your question, state t1 exist only during the propagation delay during which time the transistion in change of state has not had enough time (in nano-seconds or less) to reach the outputs, which in turn change the seconds set of inputs so the latch is now in a new state.

Given the state of the outputs as Q=1, /Q=0, changing this state is 3 delays.

  1. The delay for your change to reach the Q and/Q outputs, during which time an illogical state can exist, and is part 1 of the 'propagation' delay.

  2. The delay for the change in Q and /Q to be fed back to the RS latch. This is part 2 of the propagation delay.

  3. The delay for the cross-over feed-back to propagate though the gates internal logic and 'latch' in the new state. At this time the propagation delay is over. You are now in state t1+E with the outputs being Q=0 and /Q=1. This is in the datasheets for these parts.

  4. The designer MUST take these delays into account when building logic circuits or CPU's or MPU's, so that the next stage 'waits' a period of time longer than t1 before reading its state.

  5. Most simple 'glue' logic like this has a preset total pd time based on number of stages and the delay per stage before some down-stream logic or MPU attempts to read the results. During t1 an illogical state can and does exist for more than just NOR gates. The trick is to wait beyond t1 before reading the data.

  6. Note that this all happens at super-fast speeds. If you were to wire LED's to the Q and /Q outputs state t1 would happen much too fast for you to see.

This is from the chart at the bottom of page 2 for part 74LS02:

                    Load     15pF    50pF

                                Max     Max

tPLH Propagation Delay Time   13   18 ns  LOW-to-HIGH Level Output

tPHL Propagation Delay Time   10   15 ns  HIGH-to-LOW Level Output

This is the amount of time you MUST wait before reading the Q outputs after changing an input. Adding a safety margin would give you a 20 ns to 30 ns delay before reading Q or /Q. They are including transitions from either logic '1' or '0'.

Wiring 2 of them together to form an RS latch doubles these values because the 'feedback' loop must complete (extending t1) first before the change is stable. That means waiting about 50 ns to 60 ns before reading a change in an RS latch.

  • \$\begingroup\$ Thank you, although I still am unsure. I've updated my question with an example of where I get confused. \$\endgroup\$ Commented Jun 21, 2018 at 19:16
  • \$\begingroup\$ Why would the RS latch require a minimum propagation time for correct operation? If R/S are initially 0 and 1, the fact that S is 1 will unconditionally clear /Q independent of what Q is doing. The fact that R is low and /Q is unconditionally clear will set Q, but since S is high and /Q is already low, this will not affect anything else. After Q has become high, input S will be ignored as long as Q remains high, so it can go low whenever. If R goes high, this will cause Q to go low independent of /Q, and that will cause /Q to go low independent of S. Where is a minimum prop delay needed? \$\endgroup\$
    – supercat
    Commented Jun 21, 2018 at 20:35
  • \$\begingroup\$ @supercat. In the real-world there are delays for everything to respond to a change in input, be it NOR gates or flip-flops or inverters. I get a bit angry at how these cheap/free software simulations do not take such things into account, when they are on the parts datasheet to begin with. I grew up learning with hardware because there were no simulators during the 1970's and 1980's. That is why many events on a CPU/MPU board have to be sequenced with nops or time delays or semaphores. \$\endgroup\$
    – user105652
    Commented Jun 21, 2018 at 21:15
  • \$\begingroup\$ @Sparky256: Some kinds of circuits like edge-triggered flip flops cannot be constructed without some components that guarantee a minimum time between when an input stimulus occurs and when it may disturb the output, but I don't think the RS latch is such a circuit. So far as I can tell, if the propagation delays in an RS latch are low enough to make it stable, reducing one or both of them to zero would not affect its stability. \$\endgroup\$
    – supercat
    Commented Jun 21, 2018 at 22:10
  • \$\begingroup\$ @Sparky256 Ah, I had thought that the output value was entirely unpredictable during the propagation delay of a nor-gate (for example). It seems you are saying that the output will be stable for some portion of the gate's propagation delay. I don't see this on data sheets (e.g., futurlec.com/74LS/74LS02.shtml). Could you point me to where I can read more about this? The Wikipedia article (en.wikipedia.org/wiki/Propagation_delay) and my old textbooks) don't mention what supercat calls an "output disturb time". \$\endgroup\$ Commented Jun 21, 2018 at 22:30

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