I have a SI7460DP spice model that I would like to use in a DC DC buck\boost converter (LT8390). I'm using the standard LT spice file generated by LT powercad (boost converter going from 12 to 15V). Regardless, in a simulation as soon as I replace the mosfets with this one, the solver dies and refuses to simulate, I can leave it running overnight and I'm getting ps/s of simulation time (that means it would take 1e9 seconds to simulate 1 second of simulation, I dont' have that kind of time).

Even relaxing gmin abstol and cshunt in the simulation can't make up the difference for this model (which is poorly written).

The problem must be in the mosfet model, anybody have any idea why this model is crap and any way I can improve it?

At first glance the capacitance's are zero, that can't be a good thing as the mosfet would be switching instantaneously and confuse the solver. Most of vishays models are like this.

*Dec 10, 2012
*ECN S12-3004, Rev. C
*File Name: Si7460DP_PS.txt, Si7460DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
.SUBCKT Si7460DP 4 1 2
M1  3 1 2 2 NMOS W=5393522u L=0.25u 
M2  2 1 2 4 PMOS W=5393522u L=0.40u 
R1  4 3     RTEMP 3.3E-3
CGS 1 2     3000E-12
DBD 2 4     DBD
.MODEL  NMOS       NMOS ( LEVEL  = 3               TOX    = 7E-8
+ RS     = 4.5E-3         RD     = 0               NSUB   = 1.85E17  
+ KP     = 1.29E-5        UO     = 650             
+ VMAX   = 0              XJ     = 5E-7            KAPPA  = 1E-2
+ ETA    = 1E-4           TPG    = 1  
+ IS     = 0              LD     = 0               
+ CGSO   = 0              CGDO   = 0               CGBO   = 0 
+ NFS    = 0.8E12         DELTA  = 0.1)
.MODEL  PMOS       PMOS ( LEVEL  = 3               TOX    = 7E-8
+NSUB    = 3E16           TPG    = -1)   
.MODEL DBD D (CJO=1400E-12 VJ=0.38 M=0.36
+RS=0.1 FC=0.5 IS=1E-12 TT=5E-8 N=1 BV=60.2)
.MODEL RTEMP RES (TC1=9E-3 TC2=5.5E-6)

Source: https://www.vishay.com/docs/76626/si7460dp.zip

  • \$\begingroup\$ Yes, capacitances will help you get over hiccups most of the time. Try setting them to some pF or even less. Leave Is and Rd null, they disable the builtin body diode which doesn't have soft recovery, diodes do, with the parameter Vp (which I don't see it set, here -- strange). \$\endgroup\$ – a concerned citizen Jun 21 '18 at 19:08
  • \$\begingroup\$ They disable the diode because they have an external diode model called DBD, I'll see what setting the capacitances does \$\endgroup\$ – Voltage Spike Jun 21 '18 at 19:10
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    \$\begingroup\$ Yes, that's what I meant, the external diode is (normally) used for its soft-recovery, which the built-in diode of the VDMOS doesn't have, but here DBD doesn't have set Vp, so I find it strange why the model doesn't make use of the internal diode (in this case, since there's no soft-recovery set), which should be faster. \$\endgroup\$ – a concerned citizen Jun 21 '18 at 19:20
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    \$\begingroup\$ Try leaving it there but adding some minor capacitances. It might be there for modifying the characteristic curves. \$\endgroup\$ – a concerned citizen Jun 21 '18 at 19:31
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    \$\begingroup\$ I'm thinking tens to a few hundred pF, for the chip itself, so you could also try a few pF for the PMOS, or less, which shouldn't stand in the way but also smoothen the timestep around sharp points. Just a guess. \$\endgroup\$ – a concerned citizen Jun 21 '18 at 19:41

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