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There is some confusion here. I think that the Nios II having 32 bit data bus. Therefore, it is not capable of individual byte addressing. Therefore, the address bus increases as 0, 4, 8 e.t.c and not 0, 1, 2 e.t.c. The byte enable signal can be used to select individual byte for writing but does not have any affect on reading.

That being said, when I look at the .v files of synthesized modules after Qsys system generation, it seems that they expect the address input to increment by 1 for offset to access the different memory mapped registers, and not by 4. Here is some code from the timer core.

  assign irq = timeout_occurred && control_interrupt_enable;
  //s1, which is an e_avalon_slave
  assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
    ({16 {(address == 3)}} & period_h_register) |
    ({16 {(address == 4)}} & snap_read_value[15 : 0]) |
    ({16 {(address == 5)}} & snap_read_value[31 : 16]) |
    ({16 {(address == 1)}} & control_register) |
    ({16 {(address == 0)}} & {counter_is_running,
    timeout_occurred});

This code creates a multiplexer so we are able to read the different registers in the memory. The address offset to access the different registers is 1 and not 4. The same information is contained in the Qsys Embedded Peripherals IP User Guide. It presents a table describing the memory map, the offset values are consecutive integers.

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Edit:

The document "Making Qsys Components" found via google search is dated "October 2015" in the footer. On page 8 it says:

"Addresses used by master devices are aligned to 32-bit word boundaries. For example, Figure 8 illustrates four 32-bit addresses that could be used to select four registers in a slave device. The address of the first register is 0x10000000, the address of the second register is 0x10000004, and so on."

What is the truth?

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  • \$\begingroup\$ That "offset" for that device is in 16-bit words. So an offset of 1 is actually saying an offset 2 bytes. Nios will internally convert from byte addressing in C to word addressing with byte enable in hardware. \$\endgroup\$ – Tom Carpenter Jun 21 '18 at 20:19
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Your inference that a 32-bit data bus prohibits byte addressing is incorrect. The ARM Cortex-M, for example, has a 32-bit address bus and a 32-bit data bus but it is capable of byte reads/writes at any 32-bit address, half-word reads/writes at addresses where the least significant bit is zero, and full-word read/writes at address where the least two significant bits are zero. It's not clear from your example code, but the NiosII might allow accesses to either half-words and full-words.

The hardware knows what size object is being accessed and shifts the bytes around as necessary.

Edit: The Nios II processor uses an Avalon-MM master port for the data bus. The bus has separate enables for the four bytes in a word. A given peripheral might be designed for 16-bit registers but that does not mean that byte accesses are not possible in general. From the processor reference guide:

The processor’s data bus is 32 bits wide. Instructions are available to read and write byte, half-word (16-bit), or word (32-bit) data.

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  • \$\begingroup\$ I have updated the question with an edit so provide more information for source of my confusion. \$\endgroup\$ – quantum231 Jun 21 '18 at 19:51
  • \$\begingroup\$ For 16-bit slaves, Qsys/Platform Designer (typically used to instantiate Nios) will add "fabric" to convert the interface to 32-bit words. As far as Nios is concerned, it will interact with the device as if it was talking to a 32-bit slave. \$\endgroup\$ – Tom Carpenter Jun 21 '18 at 20:19

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