DC bias conditions are defined without any input signal. It is correct that - without any input - the output voltage will not be at zero volts (as desired).
However, with negative feedback (as shown in the diagram) the output voltage will be, most probably, not beyond 1 V.
Therefore, it is reasonable to assume Vout(DC)=0V. In this case, both resistors (Ri and Rf) are connected to ground potential and the input bias current (into the inv. terminal) goes through the parallel connection of Ri and Rf.
The error we have made in assuming Vout(DC)=0 is certainly smaller than the influence of resistor tolerances and the error we have made in assuming that both DC bias currents would be equal.
As a result - the unwanted DC voltages across the resistors caused by the DC bias currents will be approximately equal and cancel each other up to a certain degree (the input differential DC voltage at the opamp input nodes is remarkably smaller than without this bias compensation).