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In a purely synchronous design, if the design has positive slack for setup and hold times, it means that it meets timing. Therefore, provided that we have carried out static timing analysis and are happy with the slack at our targetted frequency, is there any point in carrying out post fit simulation with timing netlist anymore?

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    \$\begingroup\$ Generally, if static timing passes, you're good. Exceptions : issues with I/O signal timings (on the device pins), and chasing suspected tool (synthesis, P&R, or static timing analysis) bugs. \$\endgroup\$ – Brian Drummond Jun 23 '18 at 14:26
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Yes, post-fit timing analysis using timing netlists is necessary, assuming that you really want your design to work.

Remember that all simulations are just an approximation of the actual device behavior. Going through the process of fitting your design can change some of the routing and wiring length, because the tools don't really know how far apart your logic cells are until after they are placed. Hence, the parasitic capacitance and resistance of the wiring can change, leading to changes in propagation delay.

Every step in the design process leads you closer to the final product, so a timing analysis should be performed after each step using delay values that are extracted from the actual design. After every step your timing analysis will become more accurate because it more correctly represents the actual design.

You should always create a testbench that will check whether the design still meets all of its functional requirements. Ideally, the testbench will spit out an error message if the current simulation results differ from the previous simulation results. After every change or improvement in the design you repeat the simulation...this is called regression testing.

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  • \$\begingroup\$ But if the static timing analysis says that I have worst case positive slack at target click frequency in post fit netlist (which includes real worst case delays as far as I know), I thought that should be enough. \$\endgroup\$ – quantum231 Jun 24 '18 at 8:30
  • \$\begingroup\$ Looks like I misunderstood your question. If you have properly constrained your input signal timing, required output timing, and clock timing then a static timing check will give you a high level of confidence. Nevertheless, if you are committing an ASIC to silicon you should perform every conceivable simulation before going to fab. The analysis tools are not perfect. \$\endgroup\$ – Elliot Alderson Jun 24 '18 at 11:46

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