Is there any VHDL 93 or 2002 code that is incompatible with VHDL 2008?

In other words, if I have a bunch of files made for older vhdl standards, will a 2008 simulation/compilation work just fine?

Phrased differently, is there ANY reason NOT to use the a simulator/compiler in vhdl 2008 mode?


On the whole, VHDL 2008 reuses existing reserved words to achieve new things (without warping the syntax, they are still "good words to use" in the context).

Leafing through my copy of "VHDL-2008 - just the new stuff" some potential collisions with existing code that I noticed are:

  • Predefined maximum and minimum functions - they may collide with ones you have defined, although I imagine would function the same :)

  • There is now the functionality for force and release on signals to override their values from testbenches. Those words may collide with your code

  • New functions to_string, to_ostring and to_hstring to convert types to a natural, octal or hexdecimal string. Also a justify function.

  • New reading and writing functions: read, write, oread, owrite, hread, hwrite. Also, bread and bwrite and sread and swrite. And a flush procedure. The textio library gains a tee function.

  • The numeric_* packages gain find_leftmost and find_rightmost functions.

  • The type integer_vector is pre-defined, but again probably means the same as any type you'd already created. Also boolean_vector, real_vector, time_vector

  • A new environment package env which contains stop and finish procedures and a resolution_limit function.

The list of new reserved words is given in section 9.22: context default force parameter release

And these PSL reserved words are also reserved in VHDL2008: assert assume assume_guarantee civer fairness property restrict restrict_property sequence strong vmode vprop vunit

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In addition to Martin's list, the VHDL-93 style of shared variables are deprecated, and may have to be turned into variables of VHDL-2002/2008 protected types.

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