# Why do cascading D-Flip Flops prevent metastability?

I understand what metastability is but don't understand how linking together flip flops reduces this?

If the output of the first flipflop is metastable, this gets used as input for the second one. But I don't see how the 2nd flip flop will be able to do anything with this input and make it stable.

Metastability cannot be 'cured', but if you wait long enough, the likelihood of it occurring can be made arbitrarily small. Once you've got it down to once in the age of the universe, it's probably unlikely to cause you trouble.

It's like balancing a pencil on its point. It's likely to fall over, and the longer you wait, the less likely it is to remain standing.

There are two problems with waiting a long time, and one of them is fundamental.

The fundamental problem is that if you have a single memory element (latch or flip-flop, they both suffer from metastability) in a clocked system receiving the output from an asynchronous external system, then you physically cannot define a lower limit to the waiting time, sometimes the external signal will make a transition near the latching control edge. You have to pipeline the signal to another flip-flop to let it wait there. This gives you a guaranteed one clock cycle minimum wait time.

The second problem is that often you're trying to run a system as fast as possible, and the system clock rate cannot be slowed down to give enough time in the second flip-flop. The only way to increase the signal latency to what's necessary, without decreasing the throughput, is to pipeline the waiting to more stages.

Some people have trouble visualising what's happening between the flip-flops. There are two ways to induce metastability, and they both involve violating the flip-flop rules. One way is to violate the input setup and hold times, to make a transition when the flip-flop expects the input to be stable. The other is to violate the input logic levels, to make the flip-flop data input sit at an intermediate voltage level. A flip-flop that's being metastable can produce either type of violation on its output, to cascade on to the next flip-flop.

• As an example, back when I was doing chip design I 'owned' metastability, all the clock crossings, we did the math, figured out the chances of synchroniser failure at each flop, group of flops, etc etc looked at what the results would be ... mostly a pixel on the display might burble, in the end all the way across the chip came down to about once every two years - this was a graphics card for Win95 which at the time couldn't stay up for more than about a day we decided that no one would even notice a synchroniser 2 year MTBF. – Taniwha Jun 25 '18 at 9:48
• Also one thing that no one's mentioning is what happens with absolute worst case metastability failure ... sometimes synchroniser failure results in a flop oscillating internally at a stupidly high freq maybe at levels between the normal digital highs and lows - if it escapes your high-gain anti-metastability synchroniser flops that noisy buzzy disaster can infect all the downstream flops (as stuff fans out) resulting in huge current draws and even potentially overheating and chip-death - so do pay attention to this as an issue – Taniwha Jun 25 '18 at 9:54
• @Neil_UK You use the word latch which I think is confusing. In my circles, a latch is an asynchronous element. I'd call them flip-flops for clarity. – jalalipop Jun 26 '18 at 12:23
• @jalalipop I was using latch to mean flip-flop, though maybe its meaning has shifted in the decades since I started using it. While I agree that 'latch' generally refers to the asynchronous transparent type, they too suffer from metastability if the data changes on the 'latching' edge of the enable input. A master slave flip-flop is typically built internally from a pair of latches driven in antiphase by the clock. Thanks for mentioning it, I'll modify the answer to clarify. – Neil_UK Jun 26 '18 at 12:31
• @ Tamiwha Can you provide an answer with diagrams and time constants and the math, to make clear the internal behaviors of the latches as they try to resolve. You need to show (as you certainly know) how the loop gain and the regeneration time constant and the noise floor (thermal and VDD) affect the ability to resolve. – analogsystemsrf Jun 26 '18 at 15:05

It reduces the probability of metastability affecting the circuit by allowing more time until the signal is actually used. With two flip-flops, it allows a whole extra clock cycle for the signal to settle. With three, it allows two extra clock cycles.

• Good answer. The important point is that metastability is not prevented, we just reduce the probability to an acceptable level. – Elliot Alderson Jun 24 '18 at 22:42
• So cascading flipflops gives time for the signal to settle between 0 and 1 but it doesn't solve a wrong value? since a metastable signal can fall both ways? – Wouter A Jun 24 '18 at 22:53
• @WouterA If it's metastable then both values are right. – immibis Jun 24 '18 at 22:55
• I don't think this is a good answer, only the first flop is sampling the input signal in this case. As mentioned above what is happening is there is a probability of metastability happening (depends on the gain in the flop's internal feedback loops, clock speed and the rate the thing being sampled passes between the input thresholds) in any particular flop it's (hopefully) a small number < 1 = p - two flops give us p^2 chance of MS passing 2 flops, 3 p^3 etc etc – Taniwha Jun 25 '18 at 2:02

They don't prevent metastability from affecting the output, but they can greatly increase the mean time between incidents since the metastability would have to be of relatively long duration.

Cascading three (or more) well-designed flip-flops can increase the time between incidents to something like the age of the earth.

• Depends on your clock rate and process technology. One flip-flop might be enough for your MTBF to be infinitesimal, so long as you keep slack high. – jalalipop Jun 26 '18 at 12:28
• @jalalipop Sure. There's some actual test information (very dated now) in the original IEEE paper. DOI: 10.1109/TC.1983.1676187 – Spehro Pefhany Jun 26 '18 at 14:04
• @jalalipop: generally this is a problem that is more relevant to when you can't guarantee the slack time … aka asynchronous design, such as the FIFO that communicates between the CPU core and the SOC when the respective clocks are not phase locked. Otherwise you do just set a hard setup time and guarantee metastability will not occur. – jbord39 Sep 19 at 3:23
• Yes, Metastability is a concern on an asynchronous interface. The slack I refer to is the slack of the synchronous logic after the flip flop. If your slack is high, the Metastability event will die out before it affects the rest of your design. – jalalipop Sep 20 at 17:47

Because the first flip-flop, even if it is metastable, will have all the period of the clock to stabilize. By the time the second flip-flop samples the first flip-flop, its output could be already stable.

If you want the excitement of metastability, implement TWO VERY SLOW INVERTERS, connect them back-to-back, and bias them (in a simulation) at VDD/2. Then remove the biasing, and watch the speed of resolving to logic1 and logic0 levels. You may need to pick an initial bias voltage other than VDD/2.

If your 2 or 3 flipflops are SLOW compared to the clock period, life may be filled with problems.

Metastability simply means that, if you have a data transtion within a particular time window referenced to the clock, the output will behave badly for a certain period after the clock edge. However, the window is not a fixed interval. Rather, the likelihood of a bad value (oscillation or intermediate voltage level) declines exponentially with time. So, if you sample the signal with a clock, and then wait a bit before applying the clock to the second flip-flop, you can reduce the chances of a bad bit to any desired (but non-zero) probability. If the required time is too long, you can use 3 or more flip-flops in series.