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I have to design 3-Bit Up Synchronous Counter Using JK Flip Flop counters.

The first one should count even numbers: 0-2-4-6-0

The second one should count odd numbers: 1-3-5-7-1

Execution Table For JK Flip Flop:

Q(n) Q(n+1) J K
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0    0      0 X
0    1      1 X
1    0      X 1
1    1      X 0

First Question: Design a negative-edge-triggered synchronous counter with the form of operation: 0-2-4-6-0

My Design:

first

Second Question: Design a negative-edge-triggered synchronous counter with the form of operation: 1-3-5-7-1

My Design:

second

Main Question: I made two designs like the pictures above. But as you can see, the JK output is the same. That's weird! In both designs (even and odd) the J(C) output = Q(B) and K(C) output = Q(B). And in this case, will this odd-number circuit count by two-by-two?

Why the results are the same? Where exactly am I making a mistake?

Hint:

In the first even-counter circuit, the value of the K(A) can take 1 or 0.

In the second odd-counter circuit, the value of the J(A) can take 1 or 0.

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    \$\begingroup\$ Build up a 2-bit counter. Use it for bits 1 and 2. For bit 0, insert a jumper option to VCC or GND, depending on whether you want it to count even or odd numbers. \$\endgroup\$ Jun 25 '18 at 14:26
  • \$\begingroup\$ Thanks for that trick! But which entry of the FlipFlop will I link to? \$\endgroup\$
    – Dentrax
    Jun 25 '18 at 14:41
  • \$\begingroup\$ First the operation of a J-K flip flop...unless there's a new millennial version, JK=10 for set, 01 for reset, 11 for toggle, and 00 for no change. Does that clarify it a little? \$\endgroup\$ Jun 25 '18 at 16:31
  • \$\begingroup\$ Oh, I think you were mean Truth table. But I don't know how to design it that way. Why don't I use 3 FlipFlops? Can you give a sample design? \$\endgroup\$
    – Dentrax
    Jun 25 '18 at 17:57
  • \$\begingroup\$ Well, think of it...for a 2-bit counter, you want to toggle b0 every time, and toggle b1 only when b0 is true...if you extend further, toggle b2 only when b1 and b0 are true...see the pattern? And it's not hard to get a JK flip-flop to toggle. \$\endgroup\$ Jun 26 '18 at 12:34
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You are assuming that the even counter "wakes up" in the 000 state and the odd counter wakes up in the 001 state. Those assumptions are not valid, so some of the don't care values in your state table should actually be 0 or 1.

Other than that, take a look at the columns for the Q values in each counter. If the Q values have a similar behavior you would expect the logic design to be similar as well.

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  • \$\begingroup\$ I don't understand exactly what you said. :) Why are those assumptions not valid? 000 state for even and 001 state for odd, isn't that right? \$\endgroup\$
    – Dentrax
    Jun 25 '18 at 13:47
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In the second odd counter circuit the value of JA should be 1 (not 0) so that QA is always 1.

If you treat a k-map full of don't cares as zeros then JA = 0.

If you treat a k-map full of don't cares as ones then JA = 1.

In the first even counter circuit the value of KA should be 1 (not 0) to force the QA output to zero rather than just freezing it at whatever digital value it happens to power up at.

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