I have to design 3-bit up synchronous counter using JK flip-flops.
The first one should count even numbers:
The second one should count odd numbers:
Execution Table For JK Flip Flop:
Q(n) Q(n+1) J K --------------- 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0
First question: design a negative-edge-triggered synchronous counter with the form of operation:
Second question: Design a negative-edge-triggered synchronous counter with the form of operation:
Main question: I made two designs like the pictures above. But as you can see, the JK output is the same. That's weird! In both designs (even and odd) the J(C) output = Q(B) and K(C) output = Q(B). And in this case, will this odd-number circuit count by two-by-two?
Why are the results the same? Where exactly am I making a mistake?
In the first even-counter circuit, the value of the
K(A) can take 1 or 0.
In the second odd-counter circuit, the value of the
J(A) can take 1 or 0.