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I need to create mux block that works with inout pins. My module has n inputs and n outputs, I want to be able to switch between different outputs.

The problem that I am currently having is that I need to do that with inout pins. So if my output pin is pulled down, the input pin of the mux shall see that. This doesn't work with a common assign statement since it will only write in one direction. I have tried an alias statement, which works like a bidirectional assign, but I can not combine this with an if statement for the mux.

What I want to do:

alias net_out = (config) ? net1 : net2;

I have created an example on edaplayground

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If you are trying to model a bidirectional mux, the tranif primitives might be more appropriate/easier, depending on what your end goal is.

tranif1 #(t_on, t_off) ( a, b, ena);

so

tranif1 #(1, 1) ( net1, net2, config );

tranif0 #(1, 1) ( net2, net1, config );

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  • \$\begingroup\$ Yes thats what I am trying to do, the problem is that I do not know which port is driving at which moment, so i can not switch the direction manually. Is that a Problem with the tranif function? \$\endgroup\$ – Patrick Jun 25 '18 at 14:22
  • \$\begingroup\$ Ok, I just tried that and I can not use it with real number nets. \$\endgroup\$ – Patrick Jun 25 '18 at 14:49
  • \$\begingroup\$ tranif models a FET switch, which is directionless. The control enables the connection only. If you are trying to actively read/drive bidir signals without knowing the direction, you are going to have issues (look at bidirectional voltage translator devices to see how difficult it is) \$\endgroup\$ – GMilliorn Jun 25 '18 at 15:23
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It would have helped if you mentioned the fact that you are using real number nets to start with. SystemVerilog's tran primitives are only defined with Verilog's wire strength model, and to do what you want requires that you define your own resolution model which very few simulators have implemented yet.

More likely you are thinking in terms of analog (AMS) design and need to move up a level of abstraction to get what you want in SystemVerilog.

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  • \$\begingroup\$ I have a resolution model and a simulator that supports real number nets. My current work-around is to instantiate the blocks in a top-block and abstract the "switches" as high-Z mathematically. It is not the most elegant solution, but it works for now. \$\endgroup\$ – Patrick Jul 4 '18 at 7:29

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