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if my microstrip trace width is about 50 mil, how large should my via drill size be? Should it also be around 50 mil? Thanks!

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  • \$\begingroup\$ There are a lot of things that define via size (it usually is not critical except in certain microwave applications). What are the specifics of your application? \$\endgroup\$ – Peter Smith Jun 25 '18 at 16:42
  • \$\begingroup\$ Need to know the application and if you are trying to control impdeance \$\endgroup\$ – Voltage Spike Jun 25 '18 at 16:53
  • \$\begingroup\$ @PeterSmith The characteristic impedance is 50 ohm and the connected antenna is 900MHZ. \$\endgroup\$ – LFJY Jun 25 '18 at 17:13
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    \$\begingroup\$ The via inductance is H/D=1 related for via impedance and impedance L/C = Z^2. Follow section 20 rules too. Is this SMT type? External force? What FR4 gap? cypress.com/file/136236/download#page11 \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 25 '18 at 17:48
  • \$\begingroup\$ Are you going to use a chip antenna? or undecided? or good coax and external antenna? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 25 '18 at 19:11
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You can design your via to minimize the discontinuity it introduces in your transmission line.

Basically this means balancing the inductance introduced by the via with the capacitance between the via and other nearby conductors (such as plane layer copper, etc).

The ideal geometry won't just specify the via diameter, but also the keep-out diameter around the via, the diameter of pads on layers without connections (if used), and the location and diameter of vias for the return currents.

In addition to the required Z0, the ideal geometry will depend on the substrate Dk and which layers are being connected by the via (and thus how much stub is present on either side of the connection).

Designing the optimum geometry is generally a job for a 3-D EM simulation, although some tools (like the Saturn PCB tool) will give rough estimates.

For 900 MHz, it's unlikely that optimizing the via geometry will be needed unless you are looking for extremely low reflection coefficients in your design.

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If you have read section 20 in my comment link and read the part that it advises not to put RF on the alternate side, why are you doing that?

Understand that for std. 2 layer boards (63 mil) that 50 Ohms has a track width to ground plane gap ratio of ~1. Putting a hole in a feed track will make it necessary to recompute to the ground plane side with coplanar ground gaps.

If you plan on using SM connectors then for ground mechanical strength it may help to have microvias under pads for extra strength if needed between wide double sided ground perimeters. we can only guess since there is no layout info.

Multiple shunt microvias are better for reducing via inductance rather than a drill hole with an oversized pad , but again L/C ratio with trace length/width ratio for L and trace width/gap ratio for impedance which can use small coplanar gaps than opposite sides. This will affect your coaxial Return Loss with any antenna.

Free Saturn.exe PCB Designer tool is suggested for computing via/trace inductance and impedance at 900MHz.

It all depends on how far away you allow the signal to dropout. Any specs?

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  • \$\begingroup\$ Thanks for advice! I adjusted my layout and the direction of my antenna so that I do not need to change the layer of my microstrip. \$\endgroup\$ – LFJY Jun 25 '18 at 20:54
  • \$\begingroup\$ Make sure there are no grounds adjacent to dipole. That would reflect the energy. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 25 '18 at 21:12

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