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I have several SPI peripherals that collect data into the FPGA and I have an EBI memory module to communicate data from FPGA to micro controller. I am having a hard time understanding the best way to collect the data from the SPI peripherals and allocate it in the EBI memory. The SPI collect 16 bytes of data each and the EBI holds 8KB.

I am currently thinking that each SPI needs to have a small memory of 16*16 that once the SPIs finish collecting a memory manager would then go through each and write them into the EBI memory so once done the micro controller can collect them.

Is this over complicating, necessary or completely wrong ?

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Depends on what your space and other resource requirements are. I've written state machines and logic to generate the control signals for a SPI block because the design did not have power or space required for an on board microcontroller block (even a small one). The data was then stored in a FIFO memory block and recalled when needed elsewhere in the design by a microprocessor for data gathering.

If you can change the SPI HDL and GPIO's, you could parallel all the slave data in lines and read the data in parallel, which might make it easier to store data as it will not have to be processed serially.

Anyway, some ideas. Whatever you do, you have to look at your requirements and decide what gets the job done best, and what is the best use of resources. The resource of your time (the time it takes to write, simulate and test HDL), the resources of the FPGA (size and speed constraints), and power and timing requirements.

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  • \$\begingroup\$ Currently I am reading all spi data in parallel to the FPGA. I have EBI memory bus, similar to parallel port memory, of 16 bit data between FPGa and uController. Trying to figure out the best way to take all the SPI parallel data of 16*16bits and place in the EBI/parallel memory for the micro controller to obtain. Hardware is layed out but the HDL be changed. Should I store all the parallel SPI data in a long vector or small memory locations to be processed into the larger EBI/Parallel Port memory. It would be nice to be able load the different SPIs input into the memory location \$\endgroup\$
    – bryan
    Commented Jun 27, 2018 at 17:27
  • \$\begingroup\$ I would take each stream and process it and get the data you want, then I would load it into a register and then dump it into memory. An easier way would be to use a FIFO buffer to store the SPI values. \$\endgroup\$
    – Voltage Spike
    Commented Jun 27, 2018 at 17:45
  • \$\begingroup\$ Dumping into memory would require making the memory dual port, one for FPGA and micro controller and the other for loading internally from the SPI streams ? \$\endgroup\$
    – bryan
    Commented Jun 27, 2018 at 17:49
  • \$\begingroup\$ Depends on your FPGA, and your memory controller, you don't have to have a dual port to get data in and out, but it makes life easier \$\endgroup\$
    – Voltage Spike
    Commented Jun 27, 2018 at 18:03
  • \$\begingroup\$ Alright, thanks. I guess I was hoping there would be a way to parallel load the memory with many different devices so I can pull the data off with out delay. I am starting to see that it has to be serially loaded into the memory. I don't guess there is a way to have 10 or more ports for sub sections of my memory for each SPI device. It is currently a Spartan 6 xc6slx9. again thanks for the help. I will consider it answered unless you think I miss understood. \$\endgroup\$
    – bryan
    Commented Jun 27, 2018 at 18:10

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