Are there any effects of temperature and voltage variations on Metastability of the flip-flop? If Yes, What are the effects?
Yes, of course. Changes in supply voltage and operating temperature will change the propagation delay of all logic gates. Changes in delay will lead to changes in the setup and hold time of the flip-flop, which will in turn change the probability of metastability. All other things being the same, we would expect metastability to become more probable at higher temperature and lower supply voltage.
Changing the VDD bypass capacitance, as temperature changes, will change the VDD bounce and VDD sag; with VDD strongly affecting the transconductance of CMOS devices/flipflops, you'll have a strong temperature effect.
Also the Boltzmann/Johnson/Nyquist/thermal/random noise floor POWER is a linear function of temperature, with the noise voltage being squareroot(power).
I've seen analog comparators, in low power switching regulators, provide an apparently-oscillatory-chaotic switching behavior, when in truth the effect was just thermal-noise causing the switch-point to vary as the very slow input ramp attempted to cross the (randomly) noisy threshold.
Was this metastability? there was no flipflop attempting to resolve to rail-rail logic levels using positive feedback. There was a high-gain comparator with low input overdrive, eventually having adequate overdrive to be fully driven to rail.