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I use Vivado to program my Basys-3 card and I have a quick question about Synthesis and implementation. I noticed that when Vivado knows the inputs of an entity, it calculates the result directly and this calculation is not done on the FPGA core.

For example, I have an encryption algorithm that takes the encryption key and the plain text as input and returns the encrypted text as output, if I declare two signals equal to the key and the plain, the encryption calculation will not be done on the card but at the time of synthesis. Is there any way to disable Vivado's "behavior"?

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  • \$\begingroup\$ Why do you still have constant inputs at the time of synthesis? \$\endgroup\$ – DonFusili Jun 26 '18 at 12:45
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There are attributes that can be used to turn off bits of logic optimisation? These tools are REALLY good at eliminating unused logic and at simplifying the logic that is used, and you want them to be good at that stuff.

Attributes are somewhat implementation defined, for Vivado see UG901 chapter 2 in particular the "dont touch", and maybe the "keep" attributes.

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You can, with some effort, make the synthesis tool leave your constants alone. But I think it is a bad idea:

  1. You run the risk that the number of I/O ports exceeds your chip pin count. On some tools synthesis might still work but Place & Route will not.
  2. The logic will not be the same compared to when you add the real code to set the input signals and access the result. Your timing analysis will be off.

A method I would recommend is to add logic which makes that the tool can't remove your signals. Ideally a simple interface which sets all the input signals and reads the output signals. You don't have to actually use that interface in real life.

This post shows some code which wrote (but never tried in real life) to do this: How can I assign a 256-bit std_logic_vector input. It should even work when connected to a real SPI master interface

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